diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/startup_stm32h7a3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/startup_stm32h7a3xxq.S
new file mode 100644
index 0000000..b934572
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/startup_stm32h7a3xxq.S
@@ -0,0 +1,559 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name : startup_stm32h7a3xxq.s
+;* @author MCD Application Team
+;* Description : STM32H7xx devices vector table for MDK-ARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == Reset_Handler
+;* - Set the vector table entries with the exceptions ISR address
+;* - Branches to __main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+ PRESERVE8
+ THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+ AREA RESET, DATA, READONLY
+ EXPORT __Vectors
+ EXPORT __Vectors_End
+ EXPORT __Vectors_Size
+
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
+ DCD Reset_Handler ; Reset Handler
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update Interrupt
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI,PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA2 Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA2 Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA2 Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA2 Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA2 Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA2 Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA2 Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA2 Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LPUART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC_IRQHandler
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size EQU __Vectors_End - __Vectors
+
+ AREA |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler PROC
+ EXPORT Reset_Handler [WEAK]
+ IMPORT SystemInit
+ IMPORT __main
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__main
+ BX R0
+ ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler PROC
+ EXPORT NMI_Handler [WEAK]
+ B .
+ ENDP
+HardFault_Handler\
+ PROC
+ EXPORT HardFault_Handler [WEAK]
+ B .
+ ENDP
+MemManage_Handler\
+ PROC
+ EXPORT MemManage_Handler [WEAK]
+ B .
+ ENDP
+BusFault_Handler\
+ PROC
+ EXPORT BusFault_Handler [WEAK]
+ B .
+ ENDP
+UsageFault_Handler\
+ PROC
+ EXPORT UsageFault_Handler [WEAK]
+ B .
+ ENDP
+SVC_Handler PROC
+ EXPORT SVC_Handler [WEAK]
+ B .
+ ENDP
+DebugMon_Handler\
+ PROC
+ EXPORT DebugMon_Handler [WEAK]
+ B .
+ ENDP
+PendSV_Handler PROC
+ EXPORT PendSV_Handler [WEAK]
+ B .
+ ENDP
+SysTick_Handler PROC
+ EXPORT SysTick_Handler [WEAK]
+ B .
+ ENDP
+
+Default_Handler PROC
+
+ EXPORT WWDG_IRQHandler [WEAK]
+ EXPORT PVD_PVM_IRQHandler [WEAK]
+ EXPORT RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+ EXPORT RTC_WKUP_IRQHandler [WEAK]
+ EXPORT FLASH_IRQHandler [WEAK]
+ EXPORT RCC_IRQHandler [WEAK]
+ EXPORT EXTI0_IRQHandler [WEAK]
+ EXPORT EXTI1_IRQHandler [WEAK]
+ EXPORT EXTI2_IRQHandler [WEAK]
+ EXPORT EXTI3_IRQHandler [WEAK]
+ EXPORT EXTI4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream0_IRQHandler [WEAK]
+ EXPORT DMA1_Stream1_IRQHandler [WEAK]
+ EXPORT DMA1_Stream2_IRQHandler [WEAK]
+ EXPORT DMA1_Stream3_IRQHandler [WEAK]
+ EXPORT DMA1_Stream4_IRQHandler [WEAK]
+ EXPORT DMA1_Stream5_IRQHandler [WEAK]
+ EXPORT DMA1_Stream6_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT ADC_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT0_IRQHandler [WEAK]
+ EXPORT FDCAN1_IT1_IRQHandler [WEAK]
+ EXPORT FDCAN2_IT1_IRQHandler [WEAK]
+ EXPORT EXTI9_5_IRQHandler [WEAK]
+ EXPORT TIM1_BRK_IRQHandler [WEAK]
+ EXPORT TIM1_UP_IRQHandler [WEAK]
+ EXPORT TIM1_TRG_COM_IRQHandler [WEAK]
+ EXPORT TIM1_CC_IRQHandler [WEAK]
+ EXPORT TIM2_IRQHandler [WEAK]
+ EXPORT TIM3_IRQHandler [WEAK]
+ EXPORT TIM4_IRQHandler [WEAK]
+ EXPORT I2C1_EV_IRQHandler [WEAK]
+ EXPORT I2C1_ER_IRQHandler [WEAK]
+ EXPORT I2C2_EV_IRQHandler [WEAK]
+ EXPORT I2C2_ER_IRQHandler [WEAK]
+ EXPORT SPI1_IRQHandler [WEAK]
+ EXPORT SPI2_IRQHandler [WEAK]
+ EXPORT USART1_IRQHandler [WEAK]
+ EXPORT USART2_IRQHandler [WEAK]
+ EXPORT USART3_IRQHandler [WEAK]
+ EXPORT EXTI15_10_IRQHandler [WEAK]
+ EXPORT RTC_Alarm_IRQHandler [WEAK]
+ EXPORT DFSDM2_IRQHandler [WEAK]
+ EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
+ EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
+ EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
+ EXPORT TIM8_CC_IRQHandler [WEAK]
+ EXPORT DMA1_Stream7_IRQHandler [WEAK]
+ EXPORT FMC_IRQHandler [WEAK]
+ EXPORT SDMMC1_IRQHandler [WEAK]
+ EXPORT TIM5_IRQHandler [WEAK]
+ EXPORT SPI3_IRQHandler [WEAK]
+ EXPORT UART4_IRQHandler [WEAK]
+ EXPORT UART5_IRQHandler [WEAK]
+ EXPORT TIM6_DAC_IRQHandler [WEAK]
+ EXPORT TIM7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream0_IRQHandler [WEAK]
+ EXPORT DMA2_Stream1_IRQHandler [WEAK]
+ EXPORT DMA2_Stream2_IRQHandler [WEAK]
+ EXPORT DMA2_Stream3_IRQHandler [WEAK]
+ EXPORT DMA2_Stream4_IRQHandler [WEAK]
+ EXPORT FDCAN_CAL_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT4_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT5_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT6_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT7_IRQHandler [WEAK]
+ EXPORT DMA2_Stream5_IRQHandler [WEAK]
+ EXPORT DMA2_Stream6_IRQHandler [WEAK]
+ EXPORT DMA2_Stream7_IRQHandler [WEAK]
+ EXPORT USART6_IRQHandler [WEAK]
+ EXPORT I2C3_EV_IRQHandler [WEAK]
+ EXPORT I2C3_ER_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
+ EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
+ EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
+ EXPORT OTG_HS_IRQHandler [WEAK]
+ EXPORT DCMI_PSSI_IRQHandler [WEAK]
+ EXPORT RNG_IRQHandler [WEAK]
+ EXPORT FPU_IRQHandler [WEAK]
+ EXPORT UART7_IRQHandler [WEAK]
+ EXPORT UART8_IRQHandler [WEAK]
+ EXPORT SPI4_IRQHandler [WEAK]
+ EXPORT SPI5_IRQHandler [WEAK]
+ EXPORT SPI6_IRQHandler [WEAK]
+ EXPORT SAI1_IRQHandler [WEAK]
+ EXPORT LTDC_IRQHandler [WEAK]
+ EXPORT LTDC_ER_IRQHandler [WEAK]
+ EXPORT DMA2D_IRQHandler [WEAK]
+ EXPORT SAI2_IRQHandler [WEAK]
+ EXPORT OCTOSPI1_IRQHandler [WEAK]
+ EXPORT LPTIM1_IRQHandler [WEAK]
+ EXPORT CEC_IRQHandler [WEAK]
+ EXPORT I2C4_EV_IRQHandler [WEAK]
+ EXPORT I2C4_ER_IRQHandler [WEAK]
+ EXPORT SPDIF_RX_IRQHandler [WEAK]
+ EXPORT DMAMUX1_OVR_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT0_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT1_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT2_IRQHandler [WEAK]
+ EXPORT DFSDM1_FLT3_IRQHandler [WEAK]
+ EXPORT SWPMI1_IRQHandler [WEAK]
+ EXPORT TIM15_IRQHandler [WEAK]
+ EXPORT TIM16_IRQHandler [WEAK]
+ EXPORT TIM17_IRQHandler [WEAK]
+ EXPORT MDIOS_WKUP_IRQHandler [WEAK]
+ EXPORT MDIOS_IRQHandler [WEAK]
+ EXPORT JPEG_IRQHandler [WEAK]
+ EXPORT MDMA_IRQHandler [WEAK]
+ EXPORT SDMMC2_IRQHandler [WEAK]
+ EXPORT HSEM1_IRQHandler [WEAK]
+ EXPORT DAC2_IRQHandler [WEAK]
+ EXPORT DMAMUX2_OVR_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel0_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel1_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel2_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel3_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel4_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel5_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel6_IRQHandler [WEAK]
+ EXPORT BDMA2_Channel7_IRQHandler [WEAK]
+ EXPORT COMP_IRQHandler [WEAK]
+ EXPORT LPTIM2_IRQHandler [WEAK]
+ EXPORT LPTIM3_IRQHandler [WEAK]
+ EXPORT UART9_IRQHandler [WEAK]
+ EXPORT USART10_IRQHandler [WEAK]
+ EXPORT LPUART1_IRQHandler [WEAK]
+ EXPORT CRS_IRQHandler [WEAK]
+ EXPORT ECC_IRQHandler [WEAK]
+ EXPORT DTS_IRQHandler [WEAK]
+ EXPORT WAKEUP_PIN_IRQHandler [WEAK]
+ EXPORT OCTOSPI2_IRQHandler [WEAK]
+ EXPORT GFXMMU_IRQHandler [WEAK]
+ EXPORT BDMA1_IRQHandler [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+ B .
+
+ ENDP
+
+ ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+
+ END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/stm32h7a3xxq.sct b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/stm32h7a3xxq.sct
new file mode 100644
index 0000000..43a02f5
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_ARM/stm32h7a3xxq.sct
@@ -0,0 +1,57 @@
+#! armcc -E
+; Scatter-Loading Description File
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2016-2020 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+#include "../cmsis_nvic.h"
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+/* This value is normally defined by the tools to 0x1000 for bare metal and 0x400 for RTOS */
+#if defined(MBED_BOOT_STACK_SIZE)
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE MBED_BOOT_STACK_SIZE
+#else
+#define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) AND ~7)
+
+LR_IROM1 MBED_APP_START MBED_APP_SIZE {
+
+ ER_IROM1 MBED_APP_START MBED_APP_SIZE {
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+ RW_IRAM1 (MBED_RAM_START) { ; RW data
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - MBED_CONF_TARGET_BOOT_STACK_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16)) { ; Heap growing up
+ }
+
+ ARM_LIB_STACK (MBED_RAM_START + MBED_RAM_SIZE) EMPTY -MBED_CONF_TARGET_BOOT_STACK_SIZE { ; Stack region growing down
+ }
+}
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7a3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7a3xxq.S
new file mode 100644
index 0000000..c0d0289
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/startup_stm32h7a3xxq.S
@@ -0,0 +1,740 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32h7a3xxq.s
+ * @author MCD Application Team
+ * @brief STM32H7B3xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ *
© Copyright (c) 2019 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+ ldr r2, =_sbss
+ b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+ bl _start
+ bx lr
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_PVM_IRQHandler /* PVD/PVM through EXTI Line detection */
+ .word RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word FDCAN1_IT0_IRQHandler /* FDCAN1 interrupt line 0 */
+ .word FDCAN2_IT0_IRQHandler /* FDCAN2 interrupt line 0 */
+ .word FDCAN1_IT1_IRQHandler /* FDCAN1 interrupt line 1 */
+ .word FDCAN2_IT1_IRQHandler /* FDCAN2 interrupt line 1 */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_IRQHandler /* TIM1 Break interrupt */
+ .word TIM1_UP_IRQHandler /* TIM1 Update interrupt */
+ .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation interrupt */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word DFSDM2_IRQHandler /* DFSDM2 Interrupt */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FDCAN_CAL_IRQHandler /* FDCAN calibration unit interrupt*/
+ .word DFSDM1_FLT4_IRQHandler /* DFSDM Filter4 Interrupt */
+ .word DFSDM1_FLT5_IRQHandler /* DFSDM Filter5 Interrupt */
+ .word DFSDM1_FLT6_IRQHandler /* DFSDM Filter6 Interrupt */
+ .word DFSDM1_FLT7_IRQHandler /* DFSDM Filter7 Interrupt */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word DCMI_PSSI_IRQHandler /* DCMI, PSSI */
+ .word 0 /* Reserved */
+ .word RNG_IRQHandler /* RNG */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word SPI6_IRQHandler /* SPI6 */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word LTDC_IRQHandler /* LTDC */
+ .word LTDC_ER_IRQHandler /* LTDC error */
+ .word DMA2D_IRQHandler /* DMA2D */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word OCTOSPI1_IRQHandler /* OCTOSPI1 */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word CEC_IRQHandler /* HDMI_CEC */
+ .word I2C4_EV_IRQHandler /* I2C4 Event */
+ .word I2C4_ER_IRQHandler /* I2C4 Error */
+ .word SPDIF_RX_IRQHandler /* SPDIF_RX */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMAMUX1_OVR_IRQHandler /* DMAMUX1 Overrun interrupt */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DFSDM1_FLT0_IRQHandler /* DFSDM Filter0 Interrupt */
+ .word DFSDM1_FLT1_IRQHandler /* DFSDM Filter1 Interrupt */
+ .word DFSDM1_FLT2_IRQHandler /* DFSDM Filter2 Interrupt */
+ .word DFSDM1_FLT3_IRQHandler /* DFSDM Filter3 Interrupt */
+ .word 0 /* Reserved */
+ .word SWPMI1_IRQHandler /* Serial Wire Interface 1 global interrupt */
+ .word TIM15_IRQHandler /* TIM15 global Interrupt */
+ .word TIM16_IRQHandler /* TIM16 global Interrupt */
+ .word TIM17_IRQHandler /* TIM17 global Interrupt */
+ .word MDIOS_WKUP_IRQHandler /* MDIOS Wakeup Interrupt */
+ .word MDIOS_IRQHandler /* MDIOS global Interrupt */
+ .word JPEG_IRQHandler /* JPEG global Interrupt */
+ .word MDMA_IRQHandler /* MDMA global Interrupt */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 global Interrupt */
+ .word HSEM1_IRQHandler /* HSEM1 global Interrupt */
+ .word 0 /* Reserved */
+ .word DAC2_IRQHandler /* DAC2 global Interrupt */
+ .word DMAMUX2_OVR_IRQHandler /* DMAMUX Overrun interrupt */
+ .word BDMA2_Channel0_IRQHandler /* BDMA2 Channel 0 global Interrupt */
+ .word BDMA2_Channel1_IRQHandler /* BDMA2 Channel 1 global Interrupt */
+ .word BDMA2_Channel2_IRQHandler /* BDMA2 Channel 2 global Interrupt */
+ .word BDMA2_Channel3_IRQHandler /* BDMA2 Channel 3 global Interrupt */
+ .word BDMA2_Channel4_IRQHandler /* BDMA2 Channel 4 global Interrupt */
+ .word BDMA2_Channel5_IRQHandler /* BDMA2 Channel 5 global Interrupt */
+ .word BDMA2_Channel6_IRQHandler /* BDMA2 Channel 6 global Interrupt */
+ .word BDMA2_Channel7_IRQHandler /* BDMA2 Channel 7 global Interrupt */
+ .word COMP_IRQHandler /* COMP global Interrupt */
+ .word LPTIM2_IRQHandler /* LP TIM2 global interrupt */
+ .word LPTIM3_IRQHandler /* LP TIM3 global interrupt */
+ .word UART9_IRQHandler /* UART9 global interrupt */
+ .word USART10_IRQHandler /* USART10 global interrupt */
+ .word LPUART1_IRQHandler /* LP UART1 interrupt */
+ .word 0 /* Reserved */
+ .word CRS_IRQHandler /* Clock Recovery Global Interrupt */
+ .word ECC_IRQHandler /* ECC diagnostic Global Interrupt */
+ .word 0 /* Reserved */
+ .word DTS_IRQHandler /* DTS */
+ .word 0 /* Reserved */
+ .word WAKEUP_PIN_IRQHandler /* Interrupt for all 6 wake-up pins */
+ .word OCTOSPI2_IRQHandler /* OCTOSPI2 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word GFXMMU_IRQHandler /* GFXMMU */
+ .word BDMA1_IRQHandler /* BDMA1 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT0_IRQHandler
+ .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT0_IRQHandler
+ .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+ .weak FDCAN1_IT1_IRQHandler
+ .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+ .weak FDCAN2_IT1_IRQHandler
+ .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_IRQHandler
+ .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_IRQHandler
+ .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_IRQHandler
+ .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM2_IRQHandler
+ .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak FDCAN_CAL_IRQHandler
+ .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT4_IRQHandler
+ .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT5_IRQHandler
+ .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT6_IRQHandler
+ .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT7_IRQHandler
+ .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak DCMI_PSSI_IRQHandler
+ .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SPI6_IRQHandler
+ .thumb_set SPI6_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak LTDC_IRQHandler
+ .thumb_set LTDC_IRQHandler,Default_Handler
+
+ .weak LTDC_ER_IRQHandler
+ .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+ .weak DMA2D_IRQHandler
+ .thumb_set DMA2D_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak OCTOSPI1_IRQHandler
+ .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak CEC_IRQHandler
+ .thumb_set CEC_IRQHandler,Default_Handler
+
+ .weak I2C4_EV_IRQHandler
+ .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+ .weak I2C4_ER_IRQHandler
+ .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+ .weak SPDIF_RX_IRQHandler
+ .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+ .weak DMAMUX1_OVR_IRQHandler
+ .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TIM15_IRQHandler
+ .thumb_set TIM15_IRQHandler,Default_Handler
+
+ .weak TIM16_IRQHandler
+ .thumb_set TIM16_IRQHandler,Default_Handler
+
+ .weak TIM17_IRQHandler
+ .thumb_set TIM17_IRQHandler,Default_Handler
+
+ .weak MDIOS_WKUP_IRQHandler
+ .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+ .weak MDIOS_IRQHandler
+ .thumb_set MDIOS_IRQHandler,Default_Handler
+
+ .weak JPEG_IRQHandler
+ .thumb_set JPEG_IRQHandler,Default_Handler
+
+ .weak MDMA_IRQHandler
+ .thumb_set MDMA_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+ .weak HSEM1_IRQHandler
+ .thumb_set HSEM1_IRQHandler,Default_Handler
+
+ .weak DAC2_IRQHandler
+ .thumb_set DAC2_IRQHandler,Default_Handler
+
+ .weak DMAMUX2_OVR_IRQHandler
+ .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel0_IRQHandler
+ .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel1_IRQHandler
+ .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel2_IRQHandler
+ .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel3_IRQHandler
+ .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel4_IRQHandler
+ .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel5_IRQHandler
+ .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel6_IRQHandler
+ .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak BDMA2_Channel7_IRQHandler
+ .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak LPTIM3_IRQHandler
+ .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+ .weak LPTIM4_IRQHandler
+ .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+ .weak LPTIM5_IRQHandler
+ .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+ .weak UART9_IRQHandler
+ .thumb_set UART9_IRQHandler,Default_Handler
+
+ .weak USART10_IRQHandler
+ .thumb_set USART10_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak CRS_IRQHandler
+ .thumb_set CRS_IRQHandler,Default_Handler
+
+ .weak ECC_IRQHandler
+ .thumb_set ECC_IRQHandler,Default_Handler
+
+ .weak DTS_IRQHandler
+ .thumb_set DTS_IRQHandler,Default_Handler
+
+ .weak WAKEUP_PIN_IRQHandler
+ .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+ .weak OCTOSPI2_IRQHandler
+ .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+ .weak GFXMMU_IRQHandler
+ .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+ .weak BDMA1_IRQHandler
+ .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld
new file mode 100644
index 0000000..919077e
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_GCC_ARM/stm32h7a3xxq.ld
@@ -0,0 +1,207 @@
+/* Linker script to configure memory regions. */
+/*
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#include "../cmsis_nvic.h"
+
+
+#if !defined(MBED_APP_START)
+ #define MBED_APP_START MBED_ROM_START
+#endif
+
+#if !defined(MBED_APP_SIZE)
+ #define MBED_APP_SIZE MBED_ROM_SIZE
+#endif
+
+#if !defined(MBED_CONF_TARGET_BOOT_STACK_SIZE)
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ #define MBED_CONF_TARGET_BOOT_STACK_SIZE 0x400
+#endif
+
+/* Round up VECTORS_SIZE to 8 bytes */
+#define VECTORS_SIZE (((NVIC_NUM_VECTORS * 4) + 7) & 0xFFFFFFF8)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
+ DTCMRAM (rwx) : ORIGIN = NVIC_RAM_VECTOR_ADDRESS + VECTORS_SIZE, LENGTH = 128K - VECTORS_SIZE
+ RAM (xrw) : ORIGIN = MBED_RAM_START, LENGTH = MBED_RAM_SIZE
+ RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
+ RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
+ ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ * Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ * __exidx_start
+ * __exidx_end
+ * __etext
+ * __data_start__
+ * __preinit_array_start
+ * __preinit_array_end
+ * __init_array_start
+ * __init_array_end
+ * __fini_array_start
+ * __fini_array_end
+ * __data_end__
+ * __bss_start__
+ * __bss_end__
+ * __end__
+ * end
+ * __HeapLimit
+ * __StackLimit
+ * __StackTop
+ * __stack
+ * _estack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP(*(.isr_vector))
+ *(.text*)
+
+ KEEP(*(.init))
+ KEEP(*(.fini))
+
+ /* .ctors */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+
+ /* .dtors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.rodata*)
+
+ KEEP(*(.eh_frame*))
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ __etext = .;
+ _sidata = .;
+
+ .data : AT (__etext)
+ {
+ __data_start__ = .;
+ _sdata = .;
+ *(vtable)
+ *(.data*)
+
+ . = ALIGN(8);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(8);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(8);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP(*(SORT(.fini_array.*)))
+ KEEP(*(.fini_array))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ KEEP(*(.jcr*))
+ . = ALIGN(8);
+ /* All data end */
+ __data_end__ = .;
+ _edata = .;
+
+ } > RAM
+
+ /* Uninitialized data section
+ * This region is not initialized by the C/C++ library and can be used to
+ * store state across soft reboots. */
+ .uninitialized (NOLOAD):
+ {
+ . = ALIGN(32);
+ __uninitialized_start = .;
+ *(.uninitialized)
+ KEEP(*(.keep.uninitialized))
+ . = ALIGN(32);
+ __uninitialized_end = .;
+ } > RAM
+
+ .bss :
+ {
+ . = ALIGN(8);
+ __bss_start__ = .;
+ _sbss = .;
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(8);
+ __bss_end__ = .;
+ _ebss = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ PROVIDE(end = .);
+ *(.heap*)
+ . = ORIGIN(RAM) + LENGTH(RAM) - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later */
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > RAM
+
+ /* Set stack top to end of RAM, and stack limit move down by
+ * size of stack_dummy section */
+ __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+ _estack = __StackTop;
+ __StackLimit = __StackTop - MBED_CONF_TARGET_BOOT_STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/startup_stm32h7a3xxq.S b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/startup_stm32h7a3xxq.S
new file mode 100644
index 0000000..d0a9a14
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/startup_stm32h7a3xxq.S
@@ -0,0 +1,956 @@
+;/******************************************************************************
+; * @file startup_stm32h7a3xxq.s
+; * @author MCD Application Team
+; * @brief STM32H7B3xx devices vector table for EWARM toolchain.
+;* This module performs:
+;* - Set the initial SP
+;* - Set the initial PC == _iar_program_start,
+;* - Set the vector table entries with the exceptions ISR
+;* address.
+;* - Branches to main in the C library (which eventually
+;* calls main()).
+;* After Reset the Cortex-M processor is in Thread mode,
+;* priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* © Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;* opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION CSTACK:DATA:NOROOT(3)
+
+ SECTION .intvec:CODE:NOROOT(2)
+
+ EXTERN __iar_program_start
+ EXTERN SystemInit
+ PUBLIC __vector_table
+
+ DATA
+__vector_table
+ DCD sfe(CSTACK)
+ DCD Reset_Handler ; Reset Handler
+
+ DCD NMI_Handler ; NMI Handler
+ DCD HardFault_Handler ; Hard Fault Handler
+ DCD MemManage_Handler ; MPU Fault Handler
+ DCD BusFault_Handler ; Bus Fault Handler
+ DCD UsageFault_Handler ; Usage Fault Handler
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SVC_Handler ; SVCall Handler
+ DCD DebugMon_Handler ; Debug Monitor Handler
+ DCD 0 ; Reserved
+ DCD PendSV_Handler ; PendSV Handler
+ DCD SysTick_Handler ; SysTick Handler
+
+ ; External Interrupts
+ DCD WWDG_IRQHandler ; Window WatchDog Interrupt
+ DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection
+ DCD RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1, ADC2
+ DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt line 0
+ DCD FDCAN2_IT0_IRQHandler ; FDCAN2 interrupt line 0
+ DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt line 1
+ DCD FDCAN2_IT1_IRQHandler ; FDCAN2 interrupt line 1
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt
+ DCD TIM1_UP_IRQHandler ; TIM1 Update
+ DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation Interrupt
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD USART3_IRQHandler ; USART3
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD DFSDM2_IRQHandler ; DFSDM2 Interrupt
+ DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break Interrupt and TIM12 global interrupt
+ DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update Interrupt and TIM13 global interrupt
+ DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+ DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare Interrupt
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD FMC_IRQHandler ; FMC
+ DCD SDMMC1_IRQHandler ; SDMMC1
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD UART4_IRQHandler ; UART4
+ DCD UART5_IRQHandler ; UART5
+ DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
+ DCD TIM7_IRQHandler ; TIM7
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD FDCAN_CAL_IRQHandler ; FDCAN calibration unit interrupt
+ DCD DFSDM1_FLT4_IRQHandler ; DFSDM Filter4 Interrupt
+ DCD DFSDM1_FLT5_IRQHandler ; DFSDM Filter5 Interrupt
+ DCD DFSDM1_FLT6_IRQHandler ; DFSDM Filter6 Interrupt
+ DCD DFSDM1_FLT7_IRQHandler ; DFSDM Filter7 Interrupt
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
+ DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
+ DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
+ DCD OTG_HS_IRQHandler ; USB OTG HS
+ DCD DCMI_PSSI_IRQHandler ; DCMI, PSSI
+ DCD 0 ; Reserved
+ DCD RNG_IRQHandler ; Rng
+ DCD FPU_IRQHandler ; FPU
+ DCD UART7_IRQHandler ; UART7
+ DCD UART8_IRQHandler ; UART8
+ DCD SPI4_IRQHandler ; SPI4
+ DCD SPI5_IRQHandler ; SPI5
+ DCD SPI6_IRQHandler ; SPI6
+ DCD SAI1_IRQHandler ; SAI1
+ DCD LTDC_IRQHandler ; LTDC
+ DCD LTDC_ER_IRQHandler ; LTDC error
+ DCD DMA2D_IRQHandler ; DMA2D
+ DCD SAI2_IRQHandler ; SAI2
+ DCD OCTOSPI1_IRQHandler ; OCTOSPI1
+ DCD LPTIM1_IRQHandler ; LPTIM1
+ DCD CEC_IRQHandler ; HDMI_CEC
+ DCD I2C4_EV_IRQHandler ; I2C4 Event
+ DCD I2C4_ER_IRQHandler ; I2C4 Error
+ DCD SPDIF_RX_IRQHandler ; SPDIF_RX
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMAMUX1_OVR_IRQHandler ; DMAMUX1 Overrun interrupt
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DFSDM1_FLT0_IRQHandler ; DFSDM Filter0 Interrupt
+ DCD DFSDM1_FLT1_IRQHandler ; DFSDM Filter1 Interrupt
+ DCD DFSDM1_FLT2_IRQHandler ; DFSDM Filter2 Interrupt
+ DCD DFSDM1_FLT3_IRQHandler ; DFSDM Filter3 Interrupt
+ DCD 0 ; Reserved
+ DCD SWPMI1_IRQHandler ; Serial Wire Interface 1 global interrupt
+ DCD TIM15_IRQHandler ; TIM15 global Interrupt
+ DCD TIM16_IRQHandler ; TIM16 global Interrupt
+ DCD TIM17_IRQHandler ; TIM17 global Interrupt
+ DCD MDIOS_WKUP_IRQHandler ; MDIOS Wakeup Interrupt
+ DCD MDIOS_IRQHandler ; MDIOS global Interrupt
+ DCD JPEG_IRQHandler ; JPEG global Interrupt
+ DCD MDMA_IRQHandler ; MDMA global Interrupt
+ DCD 0 ; Reserved
+ DCD SDMMC2_IRQHandler ; SDMMC2 global Interrupt
+ DCD HSEM1_IRQHandler ; HSEM1 global Interrupt
+ DCD 0 ; Reserved
+ DCD DAC2_IRQHandler ; DAC2 global Interrupt
+ DCD DMAMUX2_OVR_IRQHandler ; DMAMUX Overrun interrupt
+ DCD BDMA2_Channel0_IRQHandler ; BDMA Channel 0 global Interrupt
+ DCD BDMA2_Channel1_IRQHandler ; BDMA Channel 1 global Interrupt
+ DCD BDMA2_Channel2_IRQHandler ; BDMA Channel 2 global Interrupt
+ DCD BDMA2_Channel3_IRQHandler ; BDMA Channel 3 global Interrupt
+ DCD BDMA2_Channel4_IRQHandler ; BDMA Channel 4 global Interrupt
+ DCD BDMA2_Channel5_IRQHandler ; BDMA Channel 5 global Interrupt
+ DCD BDMA2_Channel6_IRQHandler ; BDMA Channel 6 global Interrupt
+ DCD BDMA2_Channel7_IRQHandler ; BDMA Channel 7 global Interrupt
+ DCD COMP_IRQHandler ; COMP global Interrupt
+ DCD LPTIM2_IRQHandler ; LP TIM2 global interrupt
+ DCD LPTIM3_IRQHandler ; LP TIM3 global interrupt
+ DCD UART9_IRQHandler ; UART9 global interrupt
+ DCD USART10_IRQHandler ; USART10 global interrupt
+ DCD LPUART1_IRQHandler ; LP UART1 interrupt
+ DCD 0 ; Reserved
+ DCD CRS_IRQHandler ; Clock Recovery Global Interrupt
+ DCD ECC_IRQHandler ; ECC
+ DCD 0 ; Reserved
+ DCD DTS_IRQHandler ; DTS
+ DCD 0 ; Reserved
+ DCD WAKEUP_PIN_IRQHandler ; Interrupt for all 6 wake-up pins
+ DCD OCTOSPI2_IRQHandler ; OCTOSPI2
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD GFXMMU_IRQHandler ; GFXMMU
+ DCD BDMA1_IRQHandler ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+ THUMB
+ PUBWEAK Reset_Handler
+ SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+ LDR R0, =SystemInit
+ BLX R0
+ LDR R0, =__iar_program_start
+ BX R0
+
+ PUBWEAK NMI_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+ B NMI_Handler
+
+ PUBWEAK HardFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+ B HardFault_Handler
+
+ PUBWEAK MemManage_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+ B MemManage_Handler
+
+ PUBWEAK BusFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+ B BusFault_Handler
+
+ PUBWEAK UsageFault_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+ B UsageFault_Handler
+
+ PUBWEAK SVC_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+ B SVC_Handler
+
+ PUBWEAK DebugMon_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+ B DebugMon_Handler
+
+ PUBWEAK PendSV_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+ B PendSV_Handler
+
+ PUBWEAK SysTick_Handler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+ B SysTick_Handler
+
+ PUBWEAK WWDG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+ B WWDG_IRQHandler
+
+ PUBWEAK PVD_PVM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+ B PVD_PVM_IRQHandler
+
+ PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+ B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+ PUBWEAK RTC_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+ B RTC_WKUP_IRQHandler
+
+ PUBWEAK FLASH_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+ B FLASH_IRQHandler
+
+ PUBWEAK RCC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+ B RCC_IRQHandler
+
+ PUBWEAK EXTI0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+ B EXTI0_IRQHandler
+
+ PUBWEAK EXTI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+ B EXTI1_IRQHandler
+
+ PUBWEAK EXTI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+ B EXTI2_IRQHandler
+
+ PUBWEAK EXTI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+ B EXTI3_IRQHandler
+
+ PUBWEAK EXTI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+ B EXTI4_IRQHandler
+
+ PUBWEAK DMA1_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+ B DMA1_Stream0_IRQHandler
+
+ PUBWEAK DMA1_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+ B DMA1_Stream1_IRQHandler
+
+ PUBWEAK DMA1_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+ B DMA1_Stream2_IRQHandler
+
+ PUBWEAK DMA1_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+ B DMA1_Stream3_IRQHandler
+
+ PUBWEAK DMA1_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+ B DMA1_Stream4_IRQHandler
+
+ PUBWEAK DMA1_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+ B DMA1_Stream5_IRQHandler
+
+ PUBWEAK DMA1_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+ B DMA1_Stream6_IRQHandler
+
+ PUBWEAK ADC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+ B ADC_IRQHandler
+
+ PUBWEAK FDCAN1_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+ B FDCAN1_IT0_IRQHandler
+
+ PUBWEAK FDCAN2_IT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+ B FDCAN2_IT0_IRQHandler
+
+ PUBWEAK FDCAN1_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+ B FDCAN1_IT1_IRQHandler
+
+ PUBWEAK FDCAN2_IT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+ B FDCAN2_IT1_IRQHandler
+
+ PUBWEAK EXTI9_5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+ B EXTI9_5_IRQHandler
+
+ PUBWEAK TIM1_BRK_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+ B TIM1_BRK_IRQHandler
+
+ PUBWEAK TIM1_UP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+ B TIM1_UP_IRQHandler
+
+ PUBWEAK TIM1_TRG_COM_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+ B TIM1_TRG_COM_IRQHandler
+
+ PUBWEAK TIM1_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+ B TIM1_CC_IRQHandler
+
+ PUBWEAK TIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+ B TIM2_IRQHandler
+
+ PUBWEAK TIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+ B TIM3_IRQHandler
+
+ PUBWEAK TIM4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+ B TIM4_IRQHandler
+
+ PUBWEAK I2C1_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+ B I2C1_EV_IRQHandler
+
+ PUBWEAK I2C1_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+ B I2C1_ER_IRQHandler
+
+ PUBWEAK I2C2_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+ B I2C2_EV_IRQHandler
+
+ PUBWEAK I2C2_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+ B I2C2_ER_IRQHandler
+
+ PUBWEAK SPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+ B SPI1_IRQHandler
+
+ PUBWEAK SPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+ B SPI2_IRQHandler
+
+ PUBWEAK USART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+ B USART1_IRQHandler
+
+ PUBWEAK USART2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+ B USART2_IRQHandler
+
+ PUBWEAK USART3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+ B USART3_IRQHandler
+
+ PUBWEAK EXTI15_10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+ B EXTI15_10_IRQHandler
+
+ PUBWEAK RTC_Alarm_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+ B RTC_Alarm_IRQHandler
+
+ PUBWEAK DFSDM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+ B DFSDM2_IRQHandler
+
+ PUBWEAK TIM8_BRK_TIM12_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+ B TIM8_BRK_TIM12_IRQHandler
+
+ PUBWEAK TIM8_UP_TIM13_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+ B TIM8_UP_TIM13_IRQHandler
+
+ PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+ B TIM8_TRG_COM_TIM14_IRQHandler
+
+ PUBWEAK TIM8_CC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+ B TIM8_CC_IRQHandler
+
+ PUBWEAK DMA1_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+ B DMA1_Stream7_IRQHandler
+
+ PUBWEAK FMC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+ B FMC_IRQHandler
+
+ PUBWEAK SDMMC1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+ B SDMMC1_IRQHandler
+
+ PUBWEAK TIM5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+ B TIM5_IRQHandler
+
+ PUBWEAK SPI3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+ B SPI3_IRQHandler
+
+ PUBWEAK UART4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+ B UART4_IRQHandler
+
+ PUBWEAK UART5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+ B UART5_IRQHandler
+
+ PUBWEAK TIM6_DAC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+ B TIM6_DAC_IRQHandler
+
+ PUBWEAK TIM7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+ B TIM7_IRQHandler
+
+ PUBWEAK DMA2_Stream0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+ B DMA2_Stream0_IRQHandler
+
+ PUBWEAK DMA2_Stream1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+ B DMA2_Stream1_IRQHandler
+
+ PUBWEAK DMA2_Stream2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+ B DMA2_Stream2_IRQHandler
+
+ PUBWEAK DMA2_Stream3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+ B DMA2_Stream3_IRQHandler
+
+ PUBWEAK DMA2_Stream4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+ B DMA2_Stream4_IRQHandler
+
+ PUBWEAK FDCAN_CAL_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+ B FDCAN_CAL_IRQHandler
+
+ PUBWEAK DFSDM1_FLT4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+ B DFSDM1_FLT4_IRQHandler
+
+ PUBWEAK DFSDM1_FLT5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+ B DFSDM1_FLT5_IRQHandler
+
+ PUBWEAK DFSDM1_FLT6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+ B DFSDM1_FLT6_IRQHandler
+
+ PUBWEAK DFSDM1_FLT7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+ B DFSDM1_FLT7_IRQHandler
+
+ PUBWEAK DMA2_Stream5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+ B DMA2_Stream5_IRQHandler
+
+ PUBWEAK DMA2_Stream6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+ B DMA2_Stream6_IRQHandler
+
+ PUBWEAK DMA2_Stream7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+ B DMA2_Stream7_IRQHandler
+
+ PUBWEAK USART6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+ B USART6_IRQHandler
+
+ PUBWEAK I2C3_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+ B I2C3_EV_IRQHandler
+
+ PUBWEAK I2C3_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+ B I2C3_ER_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+ B OTG_HS_EP1_OUT_IRQHandler
+
+ PUBWEAK OTG_HS_EP1_IN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+ B OTG_HS_EP1_IN_IRQHandler
+
+ PUBWEAK OTG_HS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+ B OTG_HS_WKUP_IRQHandler
+
+ PUBWEAK OTG_HS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+ B OTG_HS_IRQHandler
+
+ PUBWEAK DCMI_PSSI_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+ B DCMI_PSSI_IRQHandler
+
+ PUBWEAK RNG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+ B RNG_IRQHandler
+
+ PUBWEAK FPU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+ B FPU_IRQHandler
+
+ PUBWEAK UART7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+ B UART7_IRQHandler
+
+ PUBWEAK UART8_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+ B UART8_IRQHandler
+
+ PUBWEAK SPI4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+ B SPI4_IRQHandler
+
+ PUBWEAK SPI5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+ B SPI5_IRQHandler
+
+ PUBWEAK SPI6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+ B SPI6_IRQHandler
+
+ PUBWEAK SAI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+ B SAI1_IRQHandler
+
+ PUBWEAK LTDC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+ B LTDC_IRQHandler
+
+ PUBWEAK LTDC_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+ B LTDC_ER_IRQHandler
+
+ PUBWEAK DMA2D_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+ B DMA2D_IRQHandler
+
+ PUBWEAK SAI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+ B SAI2_IRQHandler
+
+ PUBWEAK OCTOSPI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+ B OCTOSPI1_IRQHandler
+
+ PUBWEAK LPTIM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+ B LPTIM1_IRQHandler
+
+ PUBWEAK CEC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+ B CEC_IRQHandler
+
+ PUBWEAK I2C4_EV_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+ B I2C4_EV_IRQHandler
+
+ PUBWEAK I2C4_ER_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+ B I2C4_ER_IRQHandler
+
+ PUBWEAK SPDIF_RX_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+ B SPDIF_RX_IRQHandler
+
+ PUBWEAK DMAMUX1_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+ B DMAMUX1_OVR_IRQHandler
+
+ PUBWEAK DFSDM1_FLT0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+ B DFSDM1_FLT0_IRQHandler
+
+ PUBWEAK DFSDM1_FLT1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+ B DFSDM1_FLT1_IRQHandler
+
+ PUBWEAK DFSDM1_FLT2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+ B DFSDM1_FLT2_IRQHandler
+
+ PUBWEAK DFSDM1_FLT3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+ B DFSDM1_FLT3_IRQHandler
+
+ PUBWEAK SWPMI1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+ B SWPMI1_IRQHandler
+
+ PUBWEAK TIM15_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+ B TIM15_IRQHandler
+
+ PUBWEAK TIM16_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+ B TIM16_IRQHandler
+
+ PUBWEAK TIM17_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+ B TIM17_IRQHandler
+
+ PUBWEAK MDIOS_WKUP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+ B MDIOS_WKUP_IRQHandler
+
+ PUBWEAK MDIOS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+ B MDIOS_IRQHandler
+
+ PUBWEAK JPEG_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+ B JPEG_IRQHandler
+
+ PUBWEAK MDMA_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+ B MDMA_IRQHandler
+
+ PUBWEAK SDMMC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+ B SDMMC2_IRQHandler
+
+ PUBWEAK HSEM1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+ B HSEM1_IRQHandler
+
+ PUBWEAK DAC2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+ B DAC2_IRQHandler
+
+ PUBWEAK DMAMUX2_OVR_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+ B DMAMUX2_OVR_IRQHandler
+
+ PUBWEAK BDMA2_Channel0_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+ B BDMA2_Channel0_IRQHandler
+
+ PUBWEAK BDMA2_Channel1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+ B BDMA2_Channel1_IRQHandler
+
+ PUBWEAK BDMA2_Channel2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+ B BDMA2_Channel2_IRQHandler
+
+ PUBWEAK BDMA2_Channel3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+ B BDMA2_Channel3_IRQHandler
+
+ PUBWEAK BDMA2_Channel4_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+ B BDMA2_Channel4_IRQHandler
+
+ PUBWEAK BDMA2_Channel5_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+ B BDMA2_Channel5_IRQHandler
+
+ PUBWEAK BDMA2_Channel6_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+ B BDMA2_Channel6_IRQHandler
+
+ PUBWEAK BDMA2_Channel7_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+ B BDMA2_Channel7_IRQHandler
+
+ PUBWEAK COMP_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+ B COMP_IRQHandler
+
+ PUBWEAK LPTIM2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+ B LPTIM2_IRQHandler
+
+ PUBWEAK LPTIM3_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+ B LPTIM3_IRQHandler
+
+ PUBWEAK UART9_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+ B UART9_IRQHandler
+
+ PUBWEAK USART10_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+ B USART10_IRQHandler
+
+ PUBWEAK LPUART1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+ B LPUART1_IRQHandler
+
+ PUBWEAK CRS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+ B CRS_IRQHandler
+
+ PUBWEAK ECC_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+ B ECC_IRQHandler
+
+ PUBWEAK DTS_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+ B DTS_IRQHandler
+
+ PUBWEAK WAKEUP_PIN_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+ B WAKEUP_PIN_IRQHandler
+
+ PUBWEAK OCTOSPI2_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+ B OCTOSPI2_IRQHandler
+
+ PUBWEAK GFXMMU_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+ B GFXMMU_IRQHandler
+
+ PUBWEAK BDMA1_IRQHandler
+ SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+ B BDMA1_IRQHandler
+ END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/stm32h7a3xxq.icf b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/stm32h7a3xxq.icf
new file mode 100644
index 0000000..4bd4753
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/TOOLCHAIN_IAR/stm32h7a3xxq.icf
@@ -0,0 +1,59 @@
+/* Linker script to configure memory regions.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+/* Device specific values */
+
+/* Tools provide -DMBED_ROM_START=xxx -DMBED_ROM_SIZE=xxx -DMBED_RAM_START=xxx -DMBED_RAM_SIZE=xxx */
+
+define symbol VECTORS = 171; /* This value must match NVIC_NUM_VECTORS in cmsis_nvic.h */
+define symbol HEAP_SIZE = 0x1000;
+
+/* Common - Do not change */
+
+if (!isdefinedsymbol(MBED_APP_START)) {
+ define symbol MBED_APP_START = MBED_ROM_START;
+}
+
+if (!isdefinedsymbol(MBED_APP_SIZE)) {
+ define symbol MBED_APP_SIZE = MBED_ROM_SIZE;
+}
+
+if (!isdefinedsymbol(MBED_CONF_TARGET_BOOT_STACK_SIZE)) {
+ /* This value is normally defined by the tools
+ to 0x1000 for bare metal and 0x400 for RTOS */
+ define symbol MBED_CONF_TARGET_BOOT_STACK_SIZE = 0x400;
+}
+
+/* Round up VECTORS_SIZE to 8 bytes */
+define symbol VECTORS_SIZE = ((VECTORS * 4) + 7) & ~7;
+define symbol RAM_REGION_START = MBED_RAM_START + VECTORS_SIZE;
+define symbol RAM_REGION_SIZE = MBED_RAM_SIZE - VECTORS_SIZE;
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from MBED_APP_START size MBED_APP_SIZE];
+define region RAM_region = mem:[from RAM_REGION_START size RAM_REGION_SIZE];
+
+define block CSTACK with alignment = 8, size = MBED_CONF_TARGET_BOOT_STACK_SIZE { };
+define block HEAP with alignment = 8, size = HEAP_SIZE { };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem: MBED_APP_START { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite,
+ block CSTACK, block HEAP };
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h
new file mode 100644
index 0000000..3b2e3f7
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/cmsis_nvic.h
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ * @attention
+ *
+ * © Copyright (c) 2016-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#if !defined(MBED_ROM_START)
+#define MBED_ROM_START 0x8000000
+#endif
+
+#if !defined(MBED_ROM_SIZE)
+#define MBED_ROM_SIZE 0x200000 // 2.0 MB
+#endif
+
+#if !defined(MBED_RAM_START)
+#define MBED_RAM_START 0x24000000
+#endif
+
+#if !defined(MBED_RAM_SIZE)
+#define MBED_RAM_SIZE 0x100000 // 1.0 MB
+#endif
+
+#define NVIC_NUM_VECTORS 171
+#define NVIC_RAM_VECTOR_ADDRESS 0x20000000
+
+#endif
diff --git a/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/system_clock.c b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/system_clock.c
new file mode 100644
index 0000000..b7a34e9
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H7A3xIQ/system_clock.c
@@ -0,0 +1,200 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ *
+ * Copyright (c) 2015-2020 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+ */
+
+/**
+ * This file configures the system clock as follows:
+ *--------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 64 MHz clock)
+ *--------------------------------------------------------------------
+ * SYSCLK(MHz) | 280
+ * USB capable (48 MHz) | YES
+ *--------------------------------------------------------------------
+**/
+
+#include "stm32h7xx.h"
+#include "mbed_error.h"
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+/**
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock (MCO from STLink PCB part) */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ error("SetSysClock failed\n");
+ }
+ }
+ }
+}
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /* Supply configuration update enable */
+ HAL_PWREx_ConfigSupply(PWR_DIRECT_SMPS_SUPPLY);
+
+ /* Configure the main internal regulator output voltage */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /* Enable HSE Oscillator and activate PLL with HSE as source */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
+ if (bypass) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS;
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ }
+#if HSE_VALUE==8000000
+ RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
+ RCC_OscInitStruct.PLL.PLLN = 280; // 560 MHz
+#else
+#error Unsupported externall clock value, check HSE_VALUE define
+#endif
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 280 MHz
+ RCC_OscInitStruct.PLL.PLLQ = 56; // PLL1Q used for FDCAN = 10 MHz
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure bus clocks dividers */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 |
+ RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+#if DEVICE_USBDEVICE
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ HAL_PWREx_EnableUSBVoltageDetector();
+#endif /* DEVICE_USBDEVICE */
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+
+ /*!< Supply configuration update enable */
+ HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY);
+ /* Configure the main internal regulator output voltage */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_CSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.CSIState = RCC_CSI_OFF;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 32; // 2 MHz
+ RCC_OscInitStruct.PLL.PLLN = 280; // 560 MHz
+ RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 280 MHz
+ RCC_OscInitStruct.PLL.PLLQ = 56; // PLL1Q used for FDCAN = 10 MHz
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure bus clocks dividers */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 |
+ RCC_CLOCKTYPE_D1PCLK1 | RCC_CLOCKTYPE_D3PCLK1;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
+ RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
diff --git a/targets/targets.json b/targets/targets.json
index 60e045f..9518507 100644
--- a/targets/targets.json
+++ b/targets/targets.json
@@ -2836,6 +2836,23 @@
],
"device_name": "STM32H747XIHx"
},
+ "MCU_STM32H7A3xIQ": {
+ "inherits": [
+ "MCU_STM32H7"
+ ],
+ "public": false,
+ "core": "Cortex-M7FD",
+ "mbed_rom_start": "0x08000000",
+ "mbed_rom_size": "0x200000",
+ "mbed_ram_start": "0x24000000",
+ "mbed_ram_size": "0x100000",
+ "extra_labels_add": [
+ "STM32H7A3xIQ"
+ ],
+ "macros_add": [
+ "STM32H7A3xxQ"
+ ]
+ },
"MCU_STM32L0": {
"inherits": [
"MCU_STM32"