diff --git a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp index 90d61cb..757c12d 100644 --- a/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp +++ b/storage/blockdevice/COMPONENT_QSPIF/source/QSPIFBlockDevice.cpp @@ -1095,7 +1095,6 @@ _needs_fast_mode = true; _num_status_registers = 3; _read_status_reg_2_inst = QSPIF_INST_RDCR; - _attempt_4_byte_addressing = false; break; case 0x9d: // ISSI devices have only one status register diff --git a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_qspi.c b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_qspi.c index be14334..70e95c1 100644 --- a/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_qspi.c +++ b/targets/TARGET_STM/TARGET_STM32F7/STM32Cube_FW/STM32F7xx_HAL_Driver/stm32f7xx_hal_qspi.c @@ -571,10 +571,8 @@ __HAL_DMA_DISABLE(hqspi->hdma); } -#if defined(QSPI1_V1_0) /* Clear Busy bit */ HAL_QSPI_Abort_IT(hqspi); -#endif /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -616,10 +614,8 @@ } } -#if defined(QSPI1_V1_0) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ HAL_QSPI_Abort_IT(hqspi); -#endif /* Change state of QSPI */ hqspi->State = HAL_QSPI_STATE_READY; @@ -1021,10 +1017,8 @@ /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(QSPI1_V1_0) /* Clear Busy bit */ status = HAL_QSPI_Abort(hqspi); -#endif } } @@ -1112,10 +1106,8 @@ /* Clear Transfer Complete bit */ __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); -#if defined(QSPI1_V1_0) /* Workaround - Extra data written in the FIFO at the end of a read transfer */ status = HAL_QSPI_Abort(hqspi); -#endif } }