Workaround for Neoverse N1 erratum 1800710
Neoverse N1 erratum 1800710 is a Cat B erratum, present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the ECTLR_EL1 system register, which disables allocation of splintered pages in the L2 TLB. This errata is explained in this SDEN: https://static.docs.arm.com/sden885747/f/Arm_Neoverse_N1_MP050_Software_Developer_Errata_Notice_v21.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Ie5b15c8bc3235e474a06a57c3ec70684361857a6 |
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docs/design/cpu-specific-build-macros.rst |
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include/lib/cpus/aarch64/neoverse_n1.h |
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lib/cpus/aarch64/neoverse_n1.S |
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lib/cpus/cpu-ops.mk |
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