plat: marvell: armada: a3k: allow image load to RAM address 0

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LuminaSensum / arm-trusted-firmware

Browse code plat: marvell: armada: a3k: allow image load to RAM address 0 Marvell uses RAM address 0x0 for loading BL33 stage images. When ATF is built with DEBUG=1, its IO subsystem fails on assert checking the destination RAM address != 0. This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform allowing to bypass the above check in debug mode. Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> v2.4-LS
1 parent ff9cfdc commit 270367fbf7e2d3cb004257a7d1123fc89d58eba6 Konstantin Porotchkin authored on 27 Aug 2019 Marcin Wojtas committed on 4 Oct 2020

Browse code

Marvell uses RAM address 0x0 for loading BL33 stage images.
When ATF is built with DEBUG=1, its IO subsystem fails on
assert checking the destination RAM address != 0.
This patch adds PLAT_ALLOW_ZERO_ADDR_COPY to A3K platform
allowing to bypass the above check in debug mode.

Change-Id: I687e35cb2e9dc3166bdaa81b3904c20b784c5c6a
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

v2.4-LS

1 parent ff9cfdc commit 270367fbf7e2d3cb004257a7d1123fc89d58eba6

Konstantin Porotchkin authored on 27 Aug 2019

Marcin Wojtas committed on 4 Oct 2020

Patch

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