Workaround for Hercules erratum 1688305
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions of Hercules core. The erratum can be avoided by setting bit 1 of the implementation defined register CPUACTLR2_EL1 to 1 to prevent store- release from being dispatched before it is the oldest. Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
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docs/design/cpu-specific-build-macros.rst |
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include/lib/cpus/aarch64/cortex_hercules.h |
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lib/cpus/aarch64/cortex_hercules.S |
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lib/cpus/cpu-ops.mk |
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