GitBucket
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intel: Add bridge control for FPGA reconfig
This is to make sure that bridge access in disabled before doing full FPGA reconfiguration and turn re-enable it once the configuration succeed. Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I1f42fbf04ac1625048bbdf21b8a0443464ed833d |
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Abdul Halim, Muhammad Hadi Asyrafi
committed
on 15 Jan 2020
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| plat/intel/soc/agilex/platform.mk |
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| plat/intel/soc/common/socfpga_sip_svc.c |
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| plat/intel/soc/stratix10/platform.mk |
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