Workaround for Cortex A77 erratum 1508412
Cortex A77 erratum 1508412 is a Cat B Errata present in r0p0 and r1p0.
The workaround is a write sequence to several implementation defined
registers based on A77 revision.

This errata is explained in this SDEN:
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I217993cffb3ac57c313db8490e7b8a7bb393379b
1 parent 73740d9 commit aa3efe3df81429ef696dfe7fcb9ad9ef7ce86f6c
@laurenw-arm laurenw-arm authored on 14 Jul 2020
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docs/design/cpu-specific-build-macros.rst
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include/lib/cpus/aarch64/cortex_a77.h
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lib/cpus/cpu-ops.mk