GitBucket
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Merge changes from topic "bridge-en" into integration
* changes: intel: Add function to check fpga readiness intel: Add bridge control for FPGA reconfig intel: FPGA config_isdone() status query intel: System Manager refactoring intel: Refactor reset manager driver intel: Enable bridge access in Intel platform intel: Modify non secure access function |
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TrustedFirmware Code Review
committed
on 23 Jan 2020
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| plat/intel/soc/agilex/bl2_plat_setup.c |
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| plat/intel/soc/agilex/include/agilex_memory_controller.h |
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| plat/intel/soc/agilex/include/agilex_reset_manager.h 100644 → 0 |
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| plat/intel/soc/agilex/include/agilex_system_manager.h 100644 → 0 |
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| plat/intel/soc/agilex/include/socfpga_plat_def.h |
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| plat/intel/soc/agilex/platform.mk |
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| plat/intel/soc/agilex/soc/agilex_clock_manager.c |
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| plat/intel/soc/agilex/soc/agilex_reset_manager.c 100644 → 0 |
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| plat/intel/soc/agilex/soc/agilex_system_manager.c 100644 → 0 |
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| plat/intel/soc/common/include/socfpga_mailbox.h |
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| plat/intel/soc/common/include/socfpga_reset_manager.h |
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| plat/intel/soc/common/include/socfpga_system_manager.h 0 → 100644 |
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| plat/intel/soc/common/soc/socfpga_mailbox.c |
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| plat/intel/soc/common/soc/socfpga_reset_manager.c 0 → 100644 |
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| plat/intel/soc/common/soc/socfpga_system_manager.c 0 → 100644 |
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| plat/intel/soc/common/socfpga_psci.c |
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| plat/intel/soc/common/socfpga_sip_svc.c |
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| plat/intel/soc/stratix10/bl2_plat_setup.c |
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| plat/intel/soc/stratix10/bl31_plat_setup.c |
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| plat/intel/soc/stratix10/include/s10_memory_controller.h |
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| plat/intel/soc/stratix10/include/s10_reset_manager.h 100644 → 0 |
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| plat/intel/soc/stratix10/include/s10_system_manager.h 100644 → 0 |
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| plat/intel/soc/stratix10/include/socfpga_plat_def.h |
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| plat/intel/soc/stratix10/platform.mk |
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| plat/intel/soc/stratix10/soc/s10_clock_manager.c |
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| plat/intel/soc/stratix10/soc/s10_memory_controller.c |
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| plat/intel/soc/stratix10/soc/s10_reset_manager.c 100644 → 0 |
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| plat/intel/soc/stratix10/soc/s10_system_manager.c 100644 → 0 |
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