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xilinx: versal: Wire silicon default setup
Add new option for serial and default clock setup.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: I0ca7ad51637cdaa6bb891f22c53595d20da7236a
WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent 29af478 commit d69bbd0e80d07d4c9008a0666e192491ddf52e43
@Siva Durga Prasad Paladugu Siva Durga Prasad Paladugu authored on 3 May 2019
Jolly Shah committed on 15 Jan 2020
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plat/xilinx/versal/include/versal_def.h