Workaround for Cortex A76 erratum 1791580
Cortex A76 erratum 1791580 is a Cat B erratum present in earlier revisions of the Cortex A76. The workaround is to set a bit in the implementation defined CPUACTLR2 register, which forces atomic store operations to write-back memory to be performed in the L1 data cache. This errata is explained in this SDEN: https://static.docs.arm.com/sden885749/g/Arm_Cortex_A76_MP052_Software_Developer_Errata_Notice_v20.pdf Signed-off-by: John Powell <john.powell@arm.com> Change-Id: Iefd58159b3f2e2286138993317b98e57dc361925 |
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docs/design/cpu-specific-build-macros.rst |
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include/lib/cpus/aarch64/cortex_a76.h |
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lib/cpus/aarch64/cortex_a76.S |
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lib/cpus/cpu-ops.mk |
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