Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms

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LuminaSensum / arm-trusted-firmware

Browse code Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms Many simulation/emulation platforms do not support this hardware block leading to SErrors during register accesses. This patch conditionally accesses the registers from this block only on actual Si and FPGA platforms. Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent ceb1202 commit db891f32f6c2100beb6c7d8eedcab2df57df632f Varun Wadekar authored on 23 Mar 2018

Browse code

Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.

This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.

Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3

1 parent ceb1202 commit db891f32f6c2100beb6c7d8eedcab2df57df632f

Varun Wadekar authored on 23 Mar 2018

Patch

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Ignore Space Show notes View plat/nvidia/tegra/soc/t194/plat_psci_handlers.c

Ignore Space Show notes View plat/nvidia/tegra/soc/t194/plat_setup.c

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