If an SCP firmware is present and able to communicate via SCPI, then use
that to implement CPU and system power state transitions, including CPU
hotplug and system suspend. Otherwise, fall back to the existing CPU
power control implementation.

The last 16 KiB of SRAM A2 are reserved for the SCP firmware, and the
SCPI shared memory is at the very end of this region (and therefore the
end of SRAM A2). BL31 continues to start at the beginning of SRAM A2
(not counting the ARISC exception vector area) and fills up to the
beginning of the SCP firmware.

Because the SCP firmware is not loaded adjacent to the ARISC exception
vector area, the jump instructions used for exception handling cannot be
included in the SCP firmware image, and must be initialized here before
turning on the SCP.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Change-Id: I37b9b9636f94d4125230423726f3ac5e9cdb551c