Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU

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Browse code Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIU -PTCR is ISO client so setting it to FORCE_NON_COHERENT. -MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide ordering so no need to override from mc. -MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim so skipping it for simulation. -All the clients need to set CGID_TAG_ADR to maintain request ordering within a 4K boundary. Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent 90dce0f commit eb41fee452a8e6286a7a3369ee0b2f552d44aa2c Pritesh Raithatha authored on 1 Mar 2018 Varun Wadekar committed on 23 Jan 2020

Browse code

-PTCR is ISO client so setting it to FORCE_NON_COHERENT.
-MPCORER, MPCOREW and MIU0R/W to MIU7R/W clients itself will provide
ordering so no need to override from mc.
-MIU0R/W to MIU7R/W clients registers are not implemented in tegrasim
so skipping it for simulation.
-All the clients need to set CGID_TAG_ADR to maintain request ordering
within a 4K boundary.

Change-Id: Iaa3189a1f3e40fb4cef28be36bc4baeb5ac8f9ca
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3

1 parent 90dce0f commit eb41fee452a8e6286a7a3369ee0b2f552d44aa2c

Pritesh Raithatha authored on 1 Mar 2018

Varun Wadekar committed on 23 Jan 2020

Patch

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