Use correct type when reading SCR register

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LuminaSensum / arm-trusted-firmware

Browse code Use correct type when reading SCR register The Secure Configuration Register is 64-bits in AArch64 and 32-bits in AArch32. Use u_register_t instead of unsigned int to reflect this. Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent 262c5d3 commit f1be00da0b0acf90355558e01d5f8e1f79c0d481 Louis Mayencourt authored on 24 Jan 2020

Browse code

The Secure Configuration Register is 64-bits in AArch64 and 32-bits in
AArch32. Use u_register_t instead of unsigned int to reflect this.

Change-Id: I51b69467baba36bf0cfaec2595dc8837b1566934
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3

1 parent 262c5d3 commit f1be00da0b0acf90355558e01d5f8e1f79c0d481

Louis Mayencourt authored on 24 Jan 2020

Patch

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Ignore Space Show notes View bl31/interrupt_mgmt.c

Ignore Space Show notes View drivers/arm/gic/v3/gicv3_main.c

Ignore Space Show notes View include/bl31/interrupt_mgmt.h

Ignore Space Show notes View include/lib/el3_runtime/context_mgmt.h

Ignore Space Show notes View lib/el3_runtime/aarch64/context_mgmt.c

Ignore Space Show notes View plat/arm/common/arm_common.c

Ignore Space Show notes View plat/mediatek/mt8173/plat_pm.c

Ignore Space Show notes View plat/mediatek/mt8183/plat_pm.c

Ignore Space Show notes View plat/renesas/rcar/plat_pm.c

Ignore Space Show notes View plat/rockchip/common/plat_pm.c

Ignore Space Show notes View plat/socionext/synquacer/sq_psci.c

Ignore Space Show notes View plat/ti/k3/common/k3_psci.c

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