Neovers N1: added support to update presence of External LLC

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LuminaSensum / arm-trusted-firmware

Browse code Neovers N1: added support to update presence of External LLC CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external last level cache(LLC) in the system, the reset value is internal LLC. To cater for the platforms(like N1SDP) which has external LLC present introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be enabled by platform port. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363 WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3
1 parent 9054018 commit f2d6b4ee5740245a92fd511180f7eebc6736a80b Manish Pandey authored on 24 Jan 2020

Browse code

CPUECTLR_EL1.EXTLLC bit indicates the presense of internal or external
last level cache(LLC) in the system, the reset value is internal LLC.

To cater for the platforms(like N1SDP) which has external LLC present
introduce a new build option 'NEOVERSE_N1_EXTERNAL_LLC' which can be
enabled by platform port.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ibf475fcd6fd44401897a71600f4eafe989921363

WIP_v2.3-LS master v2.4-LS v2.3-rc2 v2.3-rc1 v2.3-rc0 v2.3

1 parent 9054018 commit f2d6b4ee5740245a92fd511180f7eebc6736a80b

Manish Pandey authored on 24 Jan 2020

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Ignore Space Show notes View docs/design/cpu-specific-build-macros.rst

Ignore Space Show notes View include/lib/cpus/aarch64/neoverse_n1.h

Ignore Space Show notes View lib/cpus/aarch64/neoverse_n1.S

Ignore Space Show notes View lib/cpus/cpu-ops.mk

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