plat: intel: Fix clock configuration bugs
This fixes a few issues on the Agilex clock configuration: - Set clock manager into boot mode before configuring clock - Fix wrong divisor used when calculating vcocalib - PLL sync configuration should be read and then written - Wait PLL lock after PLL sync configuration is done - Clear interrupt bits instead of set interrupt bits after configuration Signed-off-by: Tien Hock Loh <tien.hock.loh@intel.com> Change-Id: I54c1dc5fe9b102e3bbc1237a92d8471173b8af70 |
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plat/intel/soc/agilex/soc/agilex_clock_manager.c |
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