delay: timeout detection support ...

Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT.

timeout_init_us(some_timeout_us); returns a reference to detect
timeout for the provided microsecond delay value from current time.

timeout_elapsed(reference) return true/false whether the reference
timeout is elapsed.

Cherry picked from OP-TEE implementation [1].
  [1] commit 33d30a74502b ("core: timeout detection support")

Minor:
- Remove stm32mp platform duplicated implementation.
- Add new include in marvell ble.mk

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c

Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__ ...

NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__.

All common C compilers predefine a macro called __ASSEMBLER__ when
preprocessing a .S file. There is no reason for TF-A to define it's own
__ASSEMBLY__ macro for this purpose instead. To unify code with the
export headers (which use __ASSEMBLER__ to avoid one extra dependency),
let's deprecate __ASSEMBLY__ and switch the code base over to the
predefined standard.

Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417
Signed-off-by: Julius Werner <jwerner@chromium.org>

Update marvell platform to not rely on undefined overflow behaviour ...

This consists of ensuring that the left operand of each shift is
unsigned when the operation might overflow into the sign bit.

Change-Id: I78f386f5ac171d6e52383a3e42003e6fb3e96b57
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Remove unneeded include paths in PLAT_INCLUDES ...

Also, update platform_def.h guidelines about includes in the porting
guide.

Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Armada8k GPIO Register macro fix ...

The macro has n > 32.
It has to be n > 31 since GPIO 0-31 are on Register 0 and 32-63 on Register 1.

Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>

Sanitise includes across codebase ...

Enforce full include path for includes. Deprecate old paths.

The following folders inside include/lib have been left unchanged:

- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}

The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).

For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").

This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.

Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.

Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1700 from jwerner-chromium/JW_crashfix ...

MULTI_CONSOLE_API fixes and cleanups

drivers/console: Link console framework code by default ...

This patch makes the build system link the console framework code by
default, like it already does with other common libraries (e.g. cache
helpers). This should not make a difference in practice since TF is
linked with --gc-sections, so the linker will garbage collect all
functions and data that are not referenced by any other code. Thus, if a
platform doesn't want to include console code for size reasons and
doesn't make any references to console functions, the code will not be
included in the final binary.

To avoid compatibility issues with older platform ports, only make this
change for the MULTI_CONSOLE_API.

Change-Id: I153a9dbe680d57aadb860d1c829759ba701130d3
Signed-off-by: Julius Werner <jwerner@chromium.org>

a8k: pm: extend MSS_TRIGGER_TIMEOUT ...

Very rarely, during cpuidle operations the following error
is seen: "PM MSG Trigger Timeout".
This is caused by slow handling of message interrutps
in the PM FW running on CM3 (under heavy PM operation load).

This is not a real issue, so we extend the timeout to
avoid the error prints.

Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/59670
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

plat/marvell: comphy: Add support for SFI on Lane 4 ...

Add static configuration for SFI+ 10Gbps interface on SERDES
Lane 4.
This is just a copy of Lane 2 static values, not optimized.
Board-to-board iperf test shows up to 6Gbps transfer speed.

Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

fix: a3900: pm: fix number of CPU power switches. ...

- Number of open power switches for CPUs should be three
  and now two.

- This patch updates the value of open power switches from
  0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

svc: Update the EEPROM AVS values processing ...

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

ble: ap807: Switch to PLL mode and update CPU frequency ...

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

plat/marvell: Migrate to multi-console API ...

Migrate Marvell platforms from legacy console API to
multi-console API.

Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Standardise header guards across codebase ...

All identifiers, regardless of use, that start with two underscores are
reserved. This means they can't be used in header guards.

The style that this project is now to use the full name of the file in
capital letters followed by 'H'. For example, for a file called
"uart_example.h", the header guard is UART_EXAMPLE_H.

The exceptions are files that are imported from other projects:

- CryptoCell driver
- dt-bindings folders
- zlib headers

Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

tools: Move doimage to marvell folder for future add-ons ...

Move doimage utility from toos/doimage to tools/marvell/doimage.
This is done for supporting mode Marvell tools in the future.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

mvebu: cp110: introduce COMPHY porting layer ...

Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

marvell: Move BLE from external repo to the platform folder ...

The BLE is the pre-TF-A boot stage required by Marvell Armada
BootROM for bringing up DRAM and allow the boot image copy to it.
Since this is not a standard boot level and only uses the TF-A
as a build environment, it was introduced out of source tree.
However it turns out that such remote location introduces additional
complexity to the upstream TF-A build process.
In order to simplify the build environment the BLE source folder
is relocated from the external repository to A8K platform directory.
The build documentation is updated accordingly.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

marvell: Continue migration to new APIs ...

- Fix build issue
- Add initial memory parameters descriptors for BL2
- Migrate to image load V2

Basic build and run test passed on MacchiatoBin board.
Need to fix the service CPU (CM3) image load procesure and test
OPTEE functionality, which probably will require additional work.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

marvell: Migrate to new interfaces ...

- Migrate to bl2_early_platform_setup2().
- Remove references to removed build options.
- Use private definition of bl31_params_t.

This is an incomplete migration, the platform doesn't currently compile.

Change-Id: I1ae477b1f2489f49b651528050fdf06e4a55e425
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

drivers: i2c: mentor: move platform code into header files ...

At the moment we have two I2C stub drivers (for the Allwinner and the
Marvell platform), which #include the actual .c driver file.
Change this into the more usual design, by renaming and moving the stub
drivers into platform specific header files and including these from the
actual driver file. The platform specific include directories make sure
the driver picks up the right header automatically.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

drivers: mentor: extract MI2CV driver from Marvell driver ...

The Marvell A8K SoCs use the MI2CV IP core from Mentor Graphics, which
is also used by Allwinner.

As Mentor Graphics allows a lot of customization, the MI2CV in the two
SoC families are not compatible, and driver modifications are needed.

Extract the common code to a MI2CV driver.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>

plat: svc: ap807: add SVC configuration for AP807 ...

- add svc configuration according to values burnt
  to the chip efuse

Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: a8k: enable PMU overflow interrupt handler ...

This patch enables handling PMU overflow IRQ by GIC SPI's
directly in EL3. Also implement additional SMC routine,
which can disable the solution on demand in runtime.

Since it is possible to configure PMU interrupt trigger type
in the MADT ACPI table, it is enough to set it only once in EL3
during initialization.

Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

marvell: pm: do not panic by default in cpu_standby ...

Current default behavior of cpu_standby callback
is problematic during the SBSA test, which is
unable to run due to EL3 panic. Make it dependent on
the PM firmware running.

Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: a80x0: reconfigure CP0 PCIE0 windows ...

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: Ia8177194e542078772f90941eced81b231c16887
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: a70x0: reconfigure CP0 PCIE2 windows ...

In order to allow the use of PCIe cards such as graphics cards, whose
demands for BAR space are typically much higher than those of network
or SATA/USB cards, reconfigure the I/O windows so we can declare two
MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64
one at 0x8_0000_0000. In addition, this will leave ample room for an
ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB)

For compatibility with older kernels or firmware, leave the original
16 MB window in place as well.

Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

a8k: use the memory controller feature to protect the RT service region ...

Define the RT service space as secure with use of memory controller
trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS,
won't be able to access RT services (e.g. accidentally overwrite it,
which will at best result in RT services unavailability).

Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: rename common include file ...

Rename a8k_common.h to armada_common.h to keep the same header
name across all other Marvell Armada platforms.
This is especially useful since various Marvell platforms may
use common platform files and share the driver modules.

Change-Id: I7262105201123d54ccddef9aad4097518f1e38ef
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

Replace stdio.h functions by TF functions ...

Functions provided by stdio.h such as printf and sprintf are available
in the codebase, but they add a lot of code to the final image if they
are used:

- AArch64: ~4KB
- AArch32: ~2KB in T32, ~3KB in A32

tf_printf and tf_snprintf are a lot more simple, but it is preferable
to use them when possible because they are also used in common code.

Change-Id: Id09fd2b486198fe3d79276e2c27931595b7ba60e
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>