| 2018-07-20 |
PSCI: Fix types of definitions
...
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 20 Jul 2018
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| 2018-06-21 |
synquacer: Enable PSCI framework
...
PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Retrieve DRAM info from SCP firmware
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Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Ard Biesheuvel
authored
on 15 Jun 2018
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add SCPI driver
...
Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for various system control and power operations.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add MHU driver
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Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable MMU using xlat_tables_v2 library
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BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable System level Generic timer
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Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable GICv3 support
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synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable CCN driver support
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synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Implement topology functions
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These functions describe the layout of the cores and clusters in order
to support the PSCI framework.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Enable PL011 UART Console
...
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Add platform core management helpers
...
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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synquacer: Introduce basic platform support
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synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
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