2019-04-09 |
Checkpatch: Style fix
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Change-Id: I0cb9f0db1ef3491f55c038a10db5a88d37e89697
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Joel Hutton
committed
on 9 Apr 2019
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2019-04-08 |
cot-desc: optimise memory further
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This changes the auth_img_desc_t struct to have pointers to struct
arrays instead of struct arrays. This saves memory as many of these
were never used, and can be NULL pointers. Note the memory savings are
only when these arrays are not initialised, as it is assumed these
arrays are fixed length. A possible future optimisation could allow for
variable length.
memory diff:
bl1: bl2:
text text
-12 -12
bss bss
-1463 0
data data
-56 -48
rodata rodata
-5688 -2592
total total
-7419 -2652
Change-Id: I8f9bdedf75048b8867f40c56381e3a6dc6402bcc
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Joel Hutton
committed
on 8 Apr 2019
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Reduce memory needed for CoT description
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When Trusted Board Boot is enabled, we need to specify the Chain of
Trust (CoT) of the BL1 and BL2 images. A CoT consists of an array
of image descriptors. The authentication module assumes that each
image descriptor in this array is indexed by its unique image
identifier. For example, the Trusted Boot Firmware Certificate has to
be at index [TRUSTED_BOOT_FW_CERT_ID].
Unique image identifiers may not necessarily be consecutive. Also,
a given BL image might not use all image descriptors. For example, BL1
does not need any of the descriptors related to BL31. As a result, the
CoT array might contain holes, which unnecessarily takes up space in
the BL binary.
Using pointers to auth_img_desc_t structs (rather than structs
themselves) means these unused elements only use 1 pointer worth of
space, rather than one struct worth of space. This patch also changes
the code which accesses this array to reflect the change to pointers.
Image descriptors not needed in BL1 or BL2 respectively are also
ifdef'd out in this patch. For example, verifying the BL31 image is
the responsibility of BL2 so BL1 does not need any of the data
structures describing BL31.
memory diff:
bl1: bl2:
text text
-20 -20
bss bss
-1463 0
data data
-256 -48
rodata rodata
-5240 -1952
total total
-6979 -2020
Change-Id: I163668b174dc2b9bbb183acec817f2126864aaad
Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
Joel Hutton
committed
on 8 Apr 2019
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2019-04-03 |
Makefile: remove extra include paths in INCLUDES
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Now it is needed to use the full path of the common header files.
Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more
information.
Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 3 Apr 2019
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tzc: remove deprecated types
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Types tzc_action_t and tzc_region_attributes_t are deprecated.
Change-Id: Ieefeb8521a0e1130f39d09b5c0d2728f05084773
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 3 Apr 2019
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Console: remove deprecated finish_console_register
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The old version of the macro is deprecated.
Commit cc5859ca19ff ("Multi-console: Deprecate the
`finish_console_register` macro") provides more details.
Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 3 Apr 2019
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Merge pull request #1917 from marex/arm/master/v3meagle-v2.0.1
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rcar_gen3: plat: Add R-Car V3M support
Antonio Niño Díaz
authored
on 3 Apr 2019
GitHub
committed
on 3 Apr 2019
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2019-04-02 |
meson/gxl: Add support for SHA256 DMA engine
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In order to configure and boot SCP, BL31 has to compute and send
the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC
has a DMA facility that could be used to offload SHA-256
computations. This adds basic support of this hardware SHA-256
engine.
Signed-off-by: Remi Pommarel <repk@triplefau.lt>
Remi Pommarel
committed
on 2 Apr 2019
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rcar_gen3: plat: Add R-Car V3M support
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Add R-Car V3M support. This is based on the original
V3M support patch for Yocto v2.23.1 by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---
Marek: Update on top of mainline ATF/master
Valentine Barshak
authored
on 29 Oct 2018
Marek Vasut
committed
on 2 Apr 2019
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2019-04-01 |
rcar_gen3: drivers: qos: Add D3 QoS tables
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Add QoS tables for R-Car D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: pfc: Add D3 PFC tables
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Add PFC tables for R-Car D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: ddr_a: Add D3 DDR init
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Add R-Car D3 DDR initialization code. The code is in staging and needs
cleanup, and possibly can even be merged with the E3 init code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: swdt: Add D3 support
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Add WTCNT register configuration for the D3 SoC.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: scif: Add D3 support
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Add SCIF configuration specifics for the D3 SoC, that is detection
of the D3 SoC and SCBRR configuration.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: pwrc: Add D3 support
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The D3 SoC has one CPU core, just return 1 as a CPU number.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: drivers: rom: Mark NEW table as D3 compatible
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Add comment into the ROM driver that the new table is also D3 compatible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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rcar_gen3: plat: Add initial D3 support
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Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code
will be added separately.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut
committed
on 1 Apr 2019
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Remove several warnings reported with W=2
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Improved support for W=2 compilation flag by solving some nested-extern
and sign-compare warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed.
Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 1 Apr 2019
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Remove several warnings reported with W=1
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Improved support for W=1 compilation flag by solving missing-prototypes
and old-style-definition warnings.
The libraries are compiling with warnings (which turn into errors with
the Werror flag).
Outside of libraries, some warnings cannot be fixed without heavy
structural changes.
Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
Ambroise Vincent
committed
on 1 Apr 2019
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2019-03-22 |
driver: synosys: Fix SD MMC not initializing correctly
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dw_params.mmc_dev_type should be assigned before mmc_init, otherwise SDMMC
initialization will fail as the initialization treats the device as EMMC
instead of SD.
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 22 Mar 2019
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2019-03-13 |
Merge pull request #1879 from pbeesley-arm/pb/todo-removal
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Pb/todo removal
Soby Mathew
authored
on 13 Mar 2019
GitHub
committed
on 13 Mar 2019
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Merge pull request #1874 from hadi-asyrafi/qspi_boot
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intel: QSPI boot enablement
Soby Mathew
authored
on 13 Mar 2019
GitHub
committed
on 13 Mar 2019
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Merge pull request #1858 from thloh85-intel/dwmmc_fixes
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drivers: synopsys: Fix synopsys MMC driver
Soby Mathew
authored
on 13 Mar 2019
GitHub
committed
on 13 Mar 2019
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Merge pull request #1856 from masahisak/synquacer-scmi-support
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plat/synquacer: enable SCMI support
Soby Mathew
authored
on 13 Mar 2019
GitHub
committed
on 13 Mar 2019
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2019-03-12 |
intel: QSPI boot enablement
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Manages QSPI initialization, configuration and IO handling as boot device
Signed-off-by: Muhammad Hadi Asyrafi Abdul Halim <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Muhammad Hadi Asyrafi Abdul Halim
committed
on 12 Mar 2019
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plat/synquacer: enable SCMI support
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Enable the SCMI protocol support in SynQuacer platform.
Aside from power domain, system power and apcore management protocol,
this commit adds the vendor specific protocol(0x80).
This vendor specific protocol is used to get the dram mapping information
from SCP.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Masahisa Kojima
committed
on 12 Mar 2019
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drivers: Remove TODO from io_fip.c
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The comment suggests checking version numbers and
a checksum but there doesn't seem to be any usable
data for either of these.
For example, fip_toc_header_t doesn't contain any
version information and neither does fip_toc_entry_t.
As the function name "is_valid_header" suggests, this
function is not concerned with checksumming any of
the table of contents entries.
Change-Id: I8673ae5dd37793771760169f26b2f55c15fbf587
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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drivers: Remove TODO from io_storage
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This TODO was added five years ago so I assume that there is not
going to be a shutdown API added after all.
Change-Id: If0f4e2066454df773bd9bf41ed65d3a10248a2d3
Signed-off-by: Paul Beesley <paul.beesley@arm.com>
Paul Beesley
committed
on 12 Mar 2019
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drivers: synopsys: Fix synopsys MMC driver
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There are some issues with synopsys MMC driver:
- CMD8 should not expect data (for SD)
- ACMD51 should expect data (Send SCR for SD)
- dw_prepare should not dictate size to be MMC_BLOCK_SIZE, block size is
now handled in the dw_prepare function
- after the CMD completes, when doing dw_read, we need to invalidate cache
and wait for the data transfer to complete
- Need to set FIFO threshold, otherwise DMA might never get the interrupt
to read or write
Signed-off-by: Tien Hock, Loh <tien.hock.loh@intel.com>
Tien Hock, Loh
committed
on 12 Mar 2019
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2019-03-08 |
mmc: stm32_sdmmc2: fill ocr_voltage
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STM32MP1 SDMMC device voltage is 3.3V. We should then precise the 2 ranges
3.2 to 3.3V and 3.3 to 3.4V in ocr_voltage field.
Change-Id: I88e479f8f16bfe608a7808eace0df3fdec48deab
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 8 Mar 2019
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