2018-08-13 |
Merge pull request #1510 from robertovargas-arm/romlib
...
Add support for moving libraries to ROM
Dimitris Papastamos
authored
on 13 Aug 2018
GitHub
committed
on 13 Aug 2018
|
2018-08-10 |
drivers/mmc: Fix warning about usage of uninitialized variable
...
Because of -Werror, this causes a build error.
Change-Id: I37a8c4bbfe3f2ced5e17981a2814985919ad483b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 10 Aug 2018
|
drivers/emmc: remove emmc framework
...
Replace emmc framework by mmc framework.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
drivers/dw_mmc: migrate to mmc framework
...
Migrate dw_mmc driver from emmc framework to mmc framework. The
emmc framework will be abandoned.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
drivers/mmc: set buswidth and speed before reading data
...
It should set buswidth and speed of mmc controller before accessing
mmc.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
drivers/mmc: make mmc_ext_csd aligned with 16 char
...
DMA is always used in mmc driver. So the buffer address should
always follow the DMA limitation.
There're same requirement in mmc_read_blocks()/mmc_write_blocks()
on parameter buf. Since parameter buf comes from io_block driver,
it's already handled in io_block driver.
At here, just make the minimum address alignment on 16 chars.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
drivers/mmc: fix lba param to int
...
mmc_read_blocks()/mmc_write_blocks() derived from io_block_ops_t
type. It means that lba param should be integer type, not
unsigned integer type.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
drivers/mmc: send CMD8 only for SD card in initialization
...
Sending CMD8 before CMD1 just causes to fetch data failure in eMMC.
Check whether it's eMMC first. If it's eMMC, send CMD1 command instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 10 Aug 2018
|
Merge pull request #1505 from Yann-lms/mmc_delays
...
mmc: add required delays when retrying commands
Dimitris Papastamos
authored
on 10 Aug 2018
GitHub
committed
on 10 Aug 2018
|
2018-08-06 |
Merge pull request #1501 from robertovargas-arm/cci
...
cci: Wait before reading status register
Dimitris Papastamos
authored
on 6 Aug 2018
GitHub
committed
on 6 Aug 2018
|
2018-08-03 |
Add atexit function to libc
...
We had exit but we didn't have atexit, and we were calling panic and
tf_printf from exit, which generated a dependency from exit to them.
Having atexit allows to set a different function pointer in every image.
Change-Id: I95b9556d680d96249ed3b14da159b6f417da7661
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas
committed
on 3 Aug 2018
|
Don't include mbebtls include paths in INCLUDES
...
Mbebtls include paths are controlled by the user using the variable
MBEDTLS_DIR and they are out of the TF source tree. Since these
includes have a different origin it is better to move them to a
different variable.
This change makes easier for the romlib Makefile to parse the include
paths.
Change-Id: I3e4c99300f1012bc7f88c6b9f5bc0ec1f7b5aa8d
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas
committed
on 3 Aug 2018
|
Create a library file for libmbedtls
...
TF Makefile was linking all the objects files generated for the
Mbed TLS library instead of creating a static library that could be
used in the linking stage.
Change-Id: I8e4cd843ef56033c9d3faeee71601d110b7e4c12
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas
committed
on 3 Aug 2018
|
2018-08-02 |
mmc: add required delays when retrying commands
...
A new function mmc_reset_to_idle is also created.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Yann Gautier
committed
on 2 Aug 2018
|
2018-07-30 |
Merge pull request #1498 from glneo/cache-early-fixes
...
Early cache enable and coherency fixes
Dimitris Papastamos
authored
on 30 Jul 2018
GitHub
committed
on 30 Jul 2018
|
Fix MISRA defects in SP805 driver
...
Fix violations of MISRA C-2012 Rules 10.1, 10.3 and 10.4.
Change-Id: I13c6acda798c1666892f630f097a23e68748f9e4
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 30 Jul 2018
|
2018-07-26 |
GIC: Do not flush cache when unneeded
...
When a platform enables its caches before it initializes the
GICC/GICR interface then explicit cache maintenance is not
needed. Remove these here.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Andrew F. Davis
committed
on 26 Jul 2018
|
2018-07-24 |
stm32mp1: Add DDR support and its security with TZC400
...
The DDR driver is under dual license, BSD and GPLv2.
The configuration parameters are taken from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
stm32mp1: Add PMIC support
...
If a PMIC companion chip is present on board, it has to be configured
for regulators supplies.
This check is done with board DT configuration.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
stm32mp1: Add console support
...
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
stm32mp1: Add GPIO support
...
The management of pinctrl nodes of device tree is also added.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
stm32mp1: Add clock and reset support
...
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
Introduce STMicroelectronics STM32MP1 platform
...
STM32MP1 is a microprocessor designed by STMicroelectronics,
based on a dual Arm Cortex-A7.
It is an Armv7-A platform, using dedicated code from TF-A.
STM32MP1 uses BL2 compiled with BL2_AT_EL3.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Pascal Paillet <p.paillet@st.com>
Yann Gautier
committed
on 24 Jul 2018
|
2018-07-19 |
Merge pull request #1450 from MISL-EBU-System-SW/marvell-support-v6
...
Marvell support for Armada 8K SoC family
danh-arm
authored
on 19 Jul 2018
GitHub
committed
on 19 Jul 2018
|
cci: Wait before reading status register
...
The functions cci_enable_snoop_dvm_reqs and cci_disable_snoop_dvm_reqs write
in the SNOOP_CTRL_REGISTER of the slave interface and it polls the status
register to be sure that the operation is finished before leaving the
functions. If the write in SNOOP_CTRL_REGISTER is reordered after the first
read in the status register then these functions can finish before
enabling/disabling snoops and DVM messages.
The CCI500 TRM specifies:
Wait for the completion of the write to the Snoop Control Register
before testing the change_pending bit.
Change-Id: Idc7685963f412be1c16bcd3c6e3cca826e2fdf38
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
Roberto Vargas
committed
on 19 Jul 2018
|
2018-07-18 |
io: Allow image load to address zero
...
Remove assert on buffer address equal zero.
Marvell uses address 0x0 for loading BL33,
so this check is irrelevant and breaks the
debug builds on Marvell platforms.
Change-Id: Ie56a51138e2e4ddd8986dd7036797dc2d8b10125
Signed-off-by: Haim Boot <hayim@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/54589
Konstantin Porotchkin
committed
on 18 Jul 2018
|
marvell: drivers: Add i2c driver
...
Add i2c driver for A8K SoC family.
Change-Id: I5932b2fce286d84fc3ad5a74c4c456001faa3196
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin
committed
on 18 Jul 2018
|
mvebu: cp110: add COMPHY driver
...
Add COMPHY driver for usage in a runtime service.
Change-Id: I6fb42d0a099496d5699ee24684ae2b93ed35770b
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin
committed
on 18 Jul 2018
|
marvell: drivers: Add thermal driver
...
Add thermal driver for A8K SoC family.
The termal unit data is used by Marvell DRAM initialization
code for optimizing the memory controller configuration
Change-Id: Iad92689fa6e4224a89d872e9aa015393abd9cf73
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin
committed
on 18 Jul 2018
|
marvell: drivers: Add L3/system cache management drivers
...
Add LLC (L3) cache management drivers for Marvell SoCs
AP806, AP807 and AP810
Change-Id: Ic70710f9bc5b6b48395d62212df7011e2fbb5894
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Konstantin Porotchkin
committed
on 18 Jul 2018
|