| 2018-09-28 |
synquacer: Migrate to new interfaces
...
- Remove references to removed build options.
- Update Makefile paths.
- Migrate to bl31_early_platform_setup2().
Change-Id: I51cbf09a0297ac1ee645a959063238c9d556d8e1
Tested-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 28 Sep 2018
|
| 2018-08-30 |
Fix MISRA defects in BL31 common code
...
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 30 Aug 2018
|
| 2018-08-22 |
libc: Fix all includes in codebase
...
The codebase was using non-standard headers. It is needed to replace
them by the correct ones so that we can use the new libc headers.
Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 22 Aug 2018
|
| 2018-07-25 |
Merge pull request #1486 from antonio-nino-diaz-arm/an/psci-misra
...
Fix several MISRA defects in PSCI library
danh-arm
authored
on 25 Jul 2018
GitHub
committed
on 25 Jul 2018
|
| 2018-07-24 |
synquacer: Enable optional OP-TEE support
...
OP-TEE loading is optional on Developerbox controlled via SCP
firmware. To check if OP-TEE is loaded or not, we use DRAM1 region
info passed by SCP firmware.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Daniel Thompson <daniel.thompson@linaro.org>
Sumit Garg
committed
on 24 Jul 2018
|
| 2018-07-20 |
PSCI: Fix types of definitions
...
Also change header guards to fix defects of MISRA C-2012 Rule 21.1.
Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57
Acked-by: Sumit Garg <sumit.garg@linaro.org>
Acked-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 20 Jul 2018
|
| 2018-06-21 |
synquacer: Add platform makefile and documentation
...
Add Makefile and plaform definations file.
My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces
I've taken from their earlier work regarding build and deploy steps for
Developerbox based on Synquacer SoCs. They deserve much of the credit
for this work although, since I assembled and tested things, any blame
is probably mine.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tested-by: Daniel Thompson <daniel.thompson@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable PSCI framework
...
PSCI framework uses SCPI driver to communicate to SCP firmware for
various power management operations. Following PSCI operations are
supported:
- CPU ON
- CPU OFF
- CPU STANDBY
- SYSTEM RESET
- SYSTEM OFF
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Retrieve DRAM info from SCP firmware
...
Retrieve DRAM info from SCP firmware using SCPI driver. Board supports
multiple DRAM slots so its required to fetch DRAM info from SCP firmware
and pass this info to UEFI via non-secure SRAM.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Ard Biesheuvel
authored
on 15 Jun 2018
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Add SCPI driver
...
Add System Control and Power Interface (SCPI) driver which provides APIs
for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate
with SCP firmware for various system control and power operations.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Add MHU driver
...
Add Message Handling Unit (MHU) driver used to communicate among
Application Processors (AP) and System Control Processor (SCP).
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable MMU using xlat_tables_v2 library
...
BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable System level Generic timer
...
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable GICv3 support
...
synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable CCN driver support
...
synquacer has CCN-512 interconnect. So enable proper CCN driver
initialization.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Implement topology functions
...
These functions describe the layout of the cores and clusters in order
to support the PSCI framework.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Populate BL32 and BL33 entrypoints
...
As this platform supports direct entry to BL31 and no BL2, so
populate BL32 and BL33 entrypoints with static memory load info.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Enable PL011 UART Console
...
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Add platform core management helpers
...
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
synquacer: Introduce basic platform support
...
synquacer supports direct entry to BL31 without BL1 and BL2 as
SCP firmware does similar work. So this patch adds BL31 stub APIs.
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Sumit Garg
committed
on 21 Jun 2018
|
