juno: Remove vpath usage in platform makefile ...

As per commit bee824171189, remove all usage of the vpath keyword
in makefiles. Specify the relative paths to source files instead.

Also reorder source files in makefiles alphabetically.

Change-Id: Ic85c396f34e7a25a7239533f12bde3eed8da0ca2

juno: Fix base addresses for UART2 and UART3 ...

Also remove 'PL011_BASE' macro because it is no longer used.

Change-Id: Iefe94037cf67293b630d5256e6cac3f82abda807

juno: Rename Juno "mmap" array to avoid name confusion ...

Rename the array "mmap" in plat/juno/aarch64/plat_common.c to
"juno_mmap", to avoid confusion with the array of the same name
in lib/arch/aarch64/xlat_tables.c

Change-Id: If2f2976b1bc9177a14625a2a4559c32c5236090f

juno: Place assembler functions in separate sections ...

This extends the --gc-sections behaviour to the Juno-specific assembler
support functions in the firmware images by placing each function
into its own code section. This is achieved by using the 'func'
macro when declaring a function label.

Change-Id: I738370c0515face104531ab7944cc5bbdad49a9d

juno: Initialise UART console in all bootloader stages ...

Ensure that each bootloader stage initializes the UART console
independently. As a result, both BL3-1 and BL2 platform code now
calls console_init() instead of relying on BL1 to perform console
setup.

Also perform the console initialisation earlier in BL1 because
it must be done before it is used e.g. through a printf() call
in an assert() statement.

Change-Id: I8bb58cf1f0e42a71a01abf65da30bfa4ae533665

juno: Semihosting: Fix file mode to load binaries on Windows ...

Propagate commit 886278e55f3 on Juno.

Change-Id: I1e5e1e3c019c51af6ed54bb02fee6b1ebc201a2a

juno: Fix build further to changes on UP/MP stacks ...

These changes are necessary because of commit 2bf28e620a6.

Change-Id: I3e42e97638fe895c885bcbf44392a899284956f8

juno: Fix build further to console driver changes ...

Change-Id: I5ff5c1a6253d29fca0b271c08d74fafe33cd8f2d

juno: Fix the disable_mmu code ...

Remove the hard coding of all the MMU related registers with 0 and
disable MMU by clearing the M and C bit in SCTLR_ELx.

Also remove use of partially qualified asm helper functions.

Change-Id: I383083f93a0a53143e58f146faf7755198f6a6ca

juno: Remove use of partially qualified asm helper functions ...

Change-Id: I6d7c040d7569df601a12007dd2413c39f40f07ce

juno: Implement plat_get_syscnt_freq() function ...

In the Juno port, this function returns the first entry of the
frequency modes table from the memory mapped generic timer.

Workaround: Define BL32 base address ...

Workaround for issue #68

juno: Pull out some software components ...

On Juno, we don't need the following components so this patch
removes them of the images:
 - semihosting support;
 - FVP power controller support;
 - GICv3 support.

juno: Improve TZC-400 initialisation code ...

- Distinguish Juno specific from platform agnostic constants
 - Define constants for Juno TZC-400 NSAID

juno: Expose NIC-400 constants in the platform header file ...

It is easier to have all platform constants in the same place.

juno: Implement plat_report_exception() function ...

As for FVP platforms, Juno provides some LEDs that we can
use to report exceptions during the early boot code.

juno: BL2: Load BL30 ...

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

juno: plat_io_storage: remove semihosting ...

Removing semihosting from the plat_io_storage code copied from FVP.

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

juno: BL1: default to building bypass rom ...

Juno has a "taped out" BL1.

To run your own BL1 on the board, you have to place it in a "ROM bypass"
address and configure the platform to boot from there.

The agreed bypass address is an offset of 0x03EC0000 from the start of
NOR flash (0x08000000), which equates to 0x0BEC0000.

To run the model using a BL1 in bypass mode, you should use a parameter
set something like this:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		--data css.cluster1.cpu0=bl1.bin@0x0BEC0000 \
		-C soc.scc.apps_alt_boot=0x0BEC0000

To build BL1 as a ROM located at address zero, you can over-ride the
default value for TZROM_BASE by passing parameters to make, eg:

	ASFLAGS="-D TZROM_BASE=0x00000000" \
	CFLAGS="-D TZROM_BASE=0x00000000" \
	CROSS_COMPILE=aarch64-linux-gnu- \
	make PLAT=juno DEBUG=1 all

Then you can launch the model using a command such as:

	<path to>/FVP_CSS_Juno3 \
		-C css.aon.scp.ROMloader.fname=<SCP ROM filename> \
		-C css.trustedBootROMloader.fname=<path to>/bl1.bin \

Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>

juno: Add a handler for 'ARM Architecture' SMC calls ...

Currently UEFI and Linux are using SMC calls in the 'ARM Architecture'
Owning Entity range so lets implement these to get things working.

UEFI probably doesn't actually need to issue the ID_PRESENCE and ID_UID
calls it does, and the device-tree used by Linux could specify the PSCI
identifiers instead. After those changes, this patch isn't required.

Signed-off-by: Jon Medhurst <tixy@linaro.org>

Workaround: Setup register context for BL3-3 ...

This is a temporary solution for issue #20

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Implement PM ops to power down CPUs ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Implement PM ops to power on CPUs ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Implement SCPI Set CSS Power State command ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Add bootloader for SCP image ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Add SCPI interface and implement the SCP Ready command ...

The SCP Ready command is sent by the SCP to indicate that the BL3-0 RAM
Firmware image is successfully up and running.

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Add MHU interface ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Initialise PCIe ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Initialise TZC-400 ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>

juno: Initialise NIC-400 ...

Signed-off-by: Jon Medhurst <tixy@linaro.org>