hikey960: move out duplicated code ...

Create hikey960_bl_common.c to store duplication initialization
code in both BL1 and BL2.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: fix invoking driver init in image load driver ...

It's unnecessary to call platform driver initialization in image
load driver. We could make bl2_platform_setup() to executing
just before SCP_BL2 by setting flag IMAGE_ATTRIB_PLAT_SETUP.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: migrate to bl2_el3 ...

Since non-TF ROM is used in HiKey960 platform (Hisilicon Hi3660 SoC),
replace BL1 by BL2_EL3 in normal boot mode.

When flush images in recovery mode, keep to use BL1.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: drop LOAD_IMAGE v1 ...

Since LOAD_IMAGE_V2 is always enabled in HiKey960 platform. Drop
LOAD_IMAGE v1 to simplify code.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: fix memory overlapped in memory map ...

MAP_TSP_MEM could be either in SRAM or DRAM. When MAP_TSP_MEM is in
DRAM, it's overlapped with MAP_DDR.

Since TSP_MEM is always configured in DRAM case, it means
MAP_OPTEE_PAGEABLE is always disabled. Just remove it.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey960: avoid to dump message when fetch boardid ...

The main difference between HiKey960 v1 hardware and HiKey960 v2
hardware is on UART console.

But the function of detecting boardid dumps message before console
ready. So fix it by removing those messages.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: move out duplicated code ...

Create hikey_bl_common.c to store duplicated initialization
code in BL1 and BL2.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: migrate to bl2_el3 ...

Since non-TF ROM is used in HiKey platform (Hisilicon Hi6220 SoC),
replace BL1 by BL2_EL3 in normal boot mode.

When we recovery images in recovery mode, keep to use BL1.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: clean dcache for SRAM after initialized ...

Although SRAM is initialized, DCACHE should be cleaned too.
Because MCU is a parrallel core to access SRAM. We need to make
sure that initialized value is really written to SRAM before
MCU using it.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: drop LOAD_IMAGE v1 ...

Since LOAD_IMAGE_V2 is always enabled in HiKey platform. Drop
LOAD_IMAGE v1 to simplify code.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

hikey: fix memory overlapped in memory map ...

MAP_TSP_MEM could be either in SRAM or DRAM. When MAP_TSP_MEM is in
DRAM, it's overlapped with MAP_DDR.

Since MAP_OPTEE_PAGEABLE isn't used in SRAM case, just remove it.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

Merge pull request #1237 from sandrine-bailleux-arm/sb/spm-timer ...

SPM: Map devices in the 1st GB

SPM: Map devices in the 1st GB ...

This patch maps the devices in the first GB of the system address map
on the FVP into the S-EL1&0 translation regime when SPM support is
enabled. This grants the Secure Partition access to the devices in
this region, for example the memory-mapped Generic Timer device.

Change-Id: I3aeea65f859ecbe83efde2acee20c55500c451bc
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

hikey: fix assert in sec_protect() ...

`assert(e)` was used in place of `if (e) ERROR()` when sec_protect()
was ported from hikey fork so the logic should have been reversed.

Fixes: 3d5d9f5a ("hikey: configure the top 16MB of DRAM as secure")
Fixes: 52988b38 ("hikey: configure 4 MB of secure DRAM for OP-TEE
Secure Data Path")
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Victor Chong <victor.chong@linaro.org>

Merge pull request #1205 from petegriffin/hikey-protect-memory ...

Hikey protect optee / sdp memory

Merge pull request #1232 from masahir0y/uniphier ...

uniphier: migrate to BL2-AT-EL3

Merge pull request #1231 from Leo-Yan/hikey960_enable_fiq_handling ...

Hikey960: Enable invalid FIQ handling

Merge pull request #1223 from vchong/poplar_bl1loadsfip ...

poplar: Enable emmc and recovery build support

Merge pull request #1193 from jwerner-chromium/JW_coreboot ...

New console API and coreboot support [v4]

uniphier: switch to BL2-AT-EL3 and remove BL1 support ...

UniPhier platform implements non-TF boot ROM.  Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is entered at EL1-S.  Now, this platform is able to avoid this waste.

Enable the BL2_AT_EL3 option, and remove BL1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox ...

The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS
is disabled.

The warm boot mailbox is useless for UniPhier SoC family because BL1
is not the first image.  The UniPhier platform implements non-TF ROM,
then BL1 works as a pseudo ROM, so it is never executed in the warm
boot.

The reset vector address is not actually programmable for UniPhier
platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS
to disable the mailbox and remove pointless plat_get_my_entrypoint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

hikey: configure 4 MB of secure DRAM for OP-TEE Secure Data Path ...

Update the memory firewall configuration to reserve 4 MB of secure RAM
for use by the kernel and OP-TEE as the Secure Data Path pool.
Note that this address range (0x3E800000 - 0x3EC00000) falls in the
range already set aside by UEFI (which reserves the upper 32 MB of the
1GB DRAM for OP-TEE [1]) and was previously unused.

[1] https://github.com/96boards-hikey/edk2/blob/hikey/HisiPkg/HiKeyPkg/Library/HiKeyLib/HiKeyMem.c#L44
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

hikey: configure the top 16MB of DRAM as secure ...

DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE and should
therefore be accessible only from secure world.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

Allow API deprecation for uniphier platform ...

The `override ERROR_DEPRECATION = 1` setting in uniphier platform
makes deprecation of API difficult. Hence removing the same. This
flag should be specified on the command line if needed.

Change-Id: I8c82d8d13944e450a8cd636de3326137c04d7560
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

poplar: Add support for recovery build ...

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

poplar: Enable emmc support ...

Let bl1 and bl2 have the ability to load images from emmc instead of
dram (mmap).

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>

Hikey960: Enable invalid FIQ handling ...

When some interrupts are configured as group 0 in GICv2, these
interrupts trigger FIQ signal; this results in the Linux kernel panic
by reporting log: "Bad mode in FIQ handler detected on CPU0, code
0x00000000 -- Unknown/Uncategorized".  Unfortunately from kernel side it
has no permission to read the GIC register for group 0 interrupts so we
have no chance to get to know which interrupt is configured as secure
interrupt and cause the kernel panic.

For upper reason, this commit enables FIQ exception handling for
SPD_none case.  If the system has not enabled SPD the FIQ interrupt is
trapped into EL3 and the FIQ handler can report the interrupt number so
we can easily narrow down which FIQ introduce unexpected interrupt.
After enable SPD we can rely on SPD interrupt route model to handle FIQ.

Signed-off-by: Leo Yan <leo.yan@linaro.org>

rockchip: Move to MULTI_CONSOLE_API ...

This patch changes all Rockchip platforms to use the new
MULTI_CONSOLE_API. The platform-specific plat_crash_console
implementations are removed so that the platform can use the ones from
the common platform code instead.

Also change the registers used in plat_crash_print_regs. The existing
use of x16 and x17 has always been illegal, since those registers are
reserved for use by the linker as a temporary scratch registers in
intra-procedure-call veneers and can never be expected to maintain their
values across a function call.

Change-Id: I8249424150be8d5543ed4af93b56756795a5288f
Signed-off-by: Julius Werner <jwerner@chromium.org>

rockchip: Use coreboot-supplied serial console on coreboot systems ...

This patch changes all Rockchip platforms to initialize the serial
console with information supplied by coreboot rather than hardcoded
base address and divisor values if BL31 is run on top of coreboot.
Moving the BL2-to-BL31 parameter parsing as early as possible to ensure
that the console is available for all following code.

Also update the Rockchip platform to use MULTI_CONSOLE_API.

Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9
Signed-off-by: Julius Werner <jwerner@chromium.org>

Add default crash console code to hook up to new console API ...

This patch expands the weak stubs for the plat_crash_console_xxx
functions in common platform code to use the new console API for crash
output. This should make crash console output "just work" for most cases
without the need for the platform to explicitly set up a crash console.
For cases where the normal console framework doesn't work (e.g. very
early crashes, before the platform can register any consoles), platforms
are still able to override the functions just like before.

This feature requires the MULTI_CONSOLE_API compile-time flag to work.
For builds which don't have it set, this patch has no practical effect.

Change-Id: I80dd161cb43f9db59a0bad2dae33c6560cfac584
Signed-off-by: Julius Werner <jwerner@chromium.org>