ddr: a80x0: add DDR 32-bit mode support ...

This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.

Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>

plat: marvell: mci: perform mci link tuning for all mci interfaces ...

This commit introduces two changes:
- remove hardcoded references to mci0 from the driver
- perform mci optimization for all mci interfaces

It fixes performance issues observed on cn9132 CP2.

Change-Id: I4e040cd54ff95c9134035ac89b87d8feb28e9eba
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: mci: use more meaningful name for mci link tuning ...

The mci_initialize function name was misleading. The function itself
doesn't initialize MCI in general but performs MCI link tuning for
performance improvement.

Change-Id: I13094ad2235182a14984035bbe58013ebde84a7e
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: a8k: remove wrong or unnecessary comments ...

Change-Id: Id702c070c433f8439faad115830e71b2873ab70a
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: ap807: enable snoop filter for ap807 ...

Snoop filter needs to be enabled once per cluster.

Change-Id: I241e72f21982142ba290c7547df6f434e6a6a98d
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: ap807: update configuration space of each CP ...

By default all external CPs start with configuration address space set to
0xf200_0000. To overcome this issue, go in the loop and initialize the
CP one by one, using temporary window configuration which allows to access
each CP and update its configuration space according to decoding
windows scheme defined for each platform.

In case of cn9130 after this procedure bellow addresses will be used:
CP0 - f2000000
CP1 - f4000000
CP2 - f6000000

When the re-configuration is done there is need to restore previous
decoding window configuration(init_io_win).

Change-Id: I1a652bfbd0bf7106930a7a4e949094dc9078a981
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: add support for PLL 2.2GHz mode ...

Change-Id: Icb8fe14417665d6aadd5a5ee2b77547b4ef78773
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

plat: marvell: armada: make a8k_common.mk and mss_common.mk more generic ...

As a preparation for upcoming support for CN9130 platform, which is
classified as OcteonTx2 product but inherits functionality from a8k,
allow to use a8k_common.mk and mss_common.mk from outside of
PLAT_FAMILY_BASE.
Above is done by introducing BOARD_DIR which needs to be set by each
platform, before including a8k_common.mk and mss_common.mk. This will
allow to use mentioned mk files not only for platforms located under
previously defined PLAT_FAMILY_BASE.

Change-Id: I22356c99bc0419a40ae11e42f37acd50943ea134
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

marvell: armada: add extra level in marvell platform hierarchy ...

This commit is a preparation for upcoming support for OcteonTX and
OcteonTX2 product families. Armada platform related files (docs,
plat, include/plat) are moved to the new "armada" sub-folder.

Change-Id: Icf03356187078ad6a2e56c9870992be3ca4c9655
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Marcin Wojtas <mw@semihalf.com>