LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat

2018-06-25	Unverified f790cc0 Browse files » Merge pull request #1445 from danielboulby-arm/db/DynamicAuthentication ... Set FVP DYN_DISABLE_AUTH authentication default to 0 Dimitris Papastamos authored on 25 Jun 2018 GitHub committed on 25 Jun 2018
	5470a3c Browse files » Set FVP DYN_DISABLE_AUTH authentication default to 0 ... Set the ability to dynamically disable Trusted Boot Board authentication to be off by default Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c67529 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com> Daniel Boulby committed on 25 Jun 2018
	Unverified a455173 Browse files » Merge pull request #1448 from npoushin/npoushin/sgi575-coverity-fixes ... npoushin/sgi575 coverity fixes Dimitris Papastamos authored on 25 Jun 2018 GitHub committed on 25 Jun 2018
2018-06-23	8e26307 Browse files » plat/arm: css: Sanitize the input to css_validate_power_state ... In the case of the platform max power level being less than the system power level, make sure to not overrun the array of power states. This fixes Coverity Scan OVERRUN defect CID 267021. Change-Id: I52646ab9be2fceeb5c331b5dad7a6267991f4197 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org> Nariman Poushin committed on 23 Jun 2018
2018-06-23	9b4c611 Browse files » plat/arm: css: Convert CSS_SYSTEM_PWR_STATE from macro to inline function ... This is to fix a number of Coverity Scan DEADCODE defects, CID numbers listed below, as reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 267023 CID 267022 CID 267020 Change-Id: I2963a799b210149e84ccab5c5b9082267ddfe337 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org> Nariman Poushin committed on 23 Jun 2018
2018-06-22	Unverified c125a14 Browse files » Merge pull request #1441 from robertovargas-arm/mem_protect_board ... Move mem-protect definitions to board specific files Dimitris Papastamos authored on 22 Jun 2018 GitHub committed on 22 Jun 2018
	Unverified ebce735 Browse files » Merge pull request #1406 from robertovargas-arm/uuid ... Make TF UUID RFC 4122 compliant Dimitris Papastamos authored on 22 Jun 2018 GitHub committed on 22 Jun 2018
	Unverified 9dfd755 Browse files » Merge pull request #1437 from jeenu-arm/ras-remaining ... SDEI dispatch changes to enable RAS use cases Dimitris Papastamos authored on 22 Jun 2018 GitHub committed on 22 Jun 2018
	Unverified 520c9dd Browse files » Merge pull request #1427 from b49020/integration ... Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform. Dimitris Papastamos authored on 22 Jun 2018 GitHub committed on 22 Jun 2018
2018-06-21	a7055c5 Browse files » Arm platforms: Remove common RAS configuration source ... The file arm_ras.c intended to provide common platform-specific RAS configuration for Arm platforms. Because this file has symbol definitions, it's proving difficult to provide a common definition. This patch therefore renames and makes the file specific to FVP. Other platforms shall provide their own configuration in similar fashion. Change-Id: I766fd238946e3e49cdb659680e1b45f41b237901 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 21 Jun 2018
	Unverified ec94229 Browse files » Merge pull request #1434 from soby-mathew/sm/fix_cntfrq ... ARM Platforms: Update CNTFRQ register in CNTCTLBase frame Dimitris Papastamos authored on 21 Jun 2018 GitHub committed on 21 Jun 2018
	Unverified 0146049 Browse files » Merge pull request #1433 from sivadur/integration ... xilinx: fix zynqmp build when tsp is enabled Dimitris Papastamos authored on 21 Jun 2018 GitHub committed on 21 Jun 2018
	150c38e Browse files » synquacer: Add platform makefile and documentation ... Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Sumit Garg committed on 21 Jun 2018
	753701c Browse files » synquacer: Enable PSCI framework ... PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	cfe19f8 Browse files » synquacer: Retrieve DRAM info from SCP firmware ... Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Ard Biesheuvel authored on 15 Jun 2018 Sumit Garg committed on 21 Jun 2018
	b7ad044 Browse files » synquacer: Add SCPI driver ... Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	0537710 Browse files » synquacer: Add MHU driver ... Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	8cd37d7 Browse files » synquacer: Enable MMU using xlat_tables_v2 library ... BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	5931fda Browse files » synquacer: Enable System level Generic timer ... Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	b529799 Browse files » synquacer: Enable GICv3 support ... synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	0eb275c Browse files » synquacer: Enable CCN driver support ... synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	007a7a3 Browse files » synquacer: Implement topology functions ... These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	5e5cfc2 Browse files » synquacer: Populate BL32 and BL33 entrypoints ... As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	67b4007 Browse files » synquacer: Enable PL011 UART Console ... Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	85427de Browse files » synquacer: Add platform core management helpers ... Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	c35d59a Browse files » synquacer: Introduce basic platform support ... synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Sumit Garg committed on 21 Jun 2018
	0435ba6 Browse files » plat: xilinx: zynqmp: Get chipid from registers for BL32 ... This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Siva Durga Prasad Paladugu committed on 21 Jun 2018
	d37442f Browse files » plat: xilinx: zynqmp: Build for DDR if SPD is enabled ... This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Siva Durga Prasad Paladugu committed on 21 Jun 2018
2018-06-20	Unverified 3caa841 Browse files » Merge pull request #1403 from glneo/for-upstream-k3 ... TI K3 platform support Dimitris Papastamos authored on 20 Jun 2018 GitHub committed on 20 Jun 2018
2018-06-20	Unverified a125014 Browse files » Merge pull request #1413 from grandpaul/paulliu-rpi3-0 ... rpi3: BL32 optee support Dimitris Papastamos authored on 20 Jun 2018 GitHub committed on 20 Jun 2018