LuminaSensum/arm-trusted-firmware

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History for arm-trusted-firmware / plat

2020-10-26	6d9f9f5 Browse files » intel: mailbox: Read mailbox response even there is an error ... Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640 Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	39aebd3 Browse files » intel: mailbox: Driver now handles larger response ... This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	aad868b Browse files » intel: common: Change how mailbox handles job id & buffer ... This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
2020-10-23	941fc5c Browse files » intel: common: Improve readability of mailbox read response ... Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	1ae7b6f Browse files » intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB ... Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c Richard Gong authored on 13 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	d191eb2 Browse files » intel: common: Remove urgent from mailbox async ... Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	f8e6a09 Browse files » intel: common: Improve mailbox driver readability ... Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	516f322 Browse files » intel: common: Clean up mailbox and sip header ... Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	7f56f24 Browse files » intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a Chee Hong Ang authored on 24 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	9c28689 Browse files » Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration ... * changes: plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k plat: marvell: armada: Fix including plat/marvell/marvell.mk file plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
2020-10-22	083dbb6 Browse files » Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration Manish Pandey authored on 22 Oct 2020 TrustedFirmware Code Review committed on 22 Oct 2020
2020-10-21	d1ff30d Browse files » plat/qemu_sbsa: Remove cortex_a53 and aem_generic ... The qemu_sbsa platform uses 42bit address size but the cortex-a53 only supports 40bit addressing, the cpu is incompatible with the platform. The aem_generic is also not used with qemu_sbsa, in fact, the platform currently only properly supports the cortex-a57 cpu. Change-Id: I91c92533116f1c3451d01ca99824e91d3d58df14 Signed-off-by: Tomas Pilar <tomas@nuviateam.com> Tomas Pilar committed on 21 Oct 2020
2020-10-21	b5e3d54 Browse files » plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k ... Currently a3k target is misusing ${DOIMAGETOOL} target for building flash and UART images. It is not used for building image tool. So move ${DOIMAGETOOL} target from common marvell include file into a8k include file and add correct invocation of ${MAKE} into a3k for building flash and UART images. Part of this change is also checks that MV_DDR_PATH for a3k was specified by user as this option is required for building a3k flash and UART images. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5ae9d08b8505460933f17836c9b6435fd6e51bb6 Pali Rohár committed on 21 Oct 2020
2020-10-20	879b5b8 Browse files » plat: tc0: Configure TZC with secure world regions ... This includes configuration for SPMC and trusted OS. Change-Id: Ie24df200f446b3f5b23f5f764b115c7191e6ada3 Signed-off-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Usama Arif authored on 26 Aug 2020 Manish Pandey committed on 20 Oct 2020
	b0d1275 Browse files » plat: tc0: Enable SPMC execution at S-EL2 ... This patch enables SPMC execution at S-EL2 by adding below changes - Map TC0_MAP_TZC_DRAM1 for loading SPMC - Add details of cactus test secure partitions - Adds tc0 spmc manifest file with details on secure partitions - Inlcude TOS_FW_CONFIG when SPM is spmd - Increases bl2 image size SPMC at S-EL2 is only enabled when build with SPD=spmd. Change-Id: I4c5f70911903c232ee8ecca57f1e288d6b1cd647 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	a3ecbb3 Browse files » plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS ... - Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
	d32113c Browse files » plat: arm: Make BL32_BASE platform dependent when SPD_spmd is enabled ... To support platforms without Trusted DRAM this patch defines PLAT_ARM_SPMC_BASE and enables platform to use either Trusted DRAM or DRAM region behind TZC. Change-Id: Icaa5c7d33334258ff27e8e0bfd0812c304e68ae4 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 27 Jul 2020 Manish Pandey committed on 20 Oct 2020
	c398caf Browse files » plat: tc0: Disable SPE ... Statistical Profiling Extension is not supported by Matterhorn core Change-Id: Iec652f1c6d6b6a9bf118ba682276a7c70a6abc0d Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 28 May 2020 Manish Pandey committed on 20 Oct 2020
2020-10-19	0412b73 Browse files » plat: marvell: armada: Fix including plat/marvell/marvell.mk file ... Include file plat/marvell/marvell.mk for platform A3700 was included two times. Once from file plat/marvell/armada/a3k/common/a3700_common.mk and second time from common file plat/marvell/armada/common/marvell_common.mk. It caused following warning every time was make called: plat/marvell/marvell.mk:51: warning: overriding recipe for target 'mrvl_clean' plat/marvell/marvell.mk:51: warning: ignoring old recipe for target 'mrvl_clean' Change in this commit removes inclusion of plat/marvell/marvell.mk file in common file plat/marvell/armada/common/marvell_common.mk. As a80x0 platform needs this include file, add it also into a80x0 platform specific include file lat/marvell/armada/a8k/common/a8k_common.mk. Also moves inclusion of plat/marvell/marvell.mk file in a3700 platform file plat/marvell/armada/a3k/common/a3700_common.mk at correct place. Global plat/marvell/marvell.mk expects that variables DOIMAGEPATH and DOIMAGETOOL are already defined, but it defines MARVELL_SECURE_BOOT variable which is needed by plat/marvell/armada/a3k/common/a3700_common.mk. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I5cbbd7eb8a3376924419f9850516b2a4924be5aa Pali Rohár committed on 19 Oct 2020
2020-10-18	943aff0 Browse files » Merge "Increase type widths to satisfy width requirements" into integration Joanna Farley authored on 18 Oct 2020 TrustedFirmware Code Review committed on 18 Oct 2020
2020-10-16	4a6b33e Browse files » Merge changes Iba51bff1,I3f563cff into integration ... * changes: plat:qti Mandate SMC implementaion and bug fix Update in coreboot_get_memory_type API to include size as well Madhukar Pappireddy authored on 16 Oct 2020 TrustedFirmware Code Review committed on 16 Oct 2020
2020-10-15	4b91845 Browse files » plat:qti Mandate SMC implementaion and bug fix ... implementation of SMC call SMCCC_ARCH_SOC_ID adding debugging logs in mem assign call. Checking range of param in mem_assign call is from CB_MEM_RAM or CB_MEM_RESERVED. Change-Id: Iba51bff154df01e02dcb7715582ffaff7beba26e Signed-off-by: Saurabh Gorecha <sgorecha@codeaurora.org> Saurabh Gorecha committed on 15 Oct 2020
2020-10-15	c5e1b06 Browse files » plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it ... Some of targets (e.g. mrvl_flash) depends on WTP build option. Other targets (e.g. fip) can be build also without WTP build option as they do not depend on it. This change put all A3720 variables and targets which depends on WTP into conditional if-endif section, so they are not defined when user has not supplied WTP build option. Target mrvl_flash is defined also when WTP was not specified and in this case it just print error message to help user. Variables which do not depend on WTP are moved to the top of a3700_common.mk file. Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: Idb3892233586a0afca3e0e6564279641d2e4b960 Pali Rohár committed on 15 Oct 2020
2020-10-14	dfe577a Browse files » Merge "Don't return error information from console_flush" into integration Mark Dykes authored on 14 Oct 2020 TrustedFirmware Code Review committed on 14 Oct 2020
2020-10-13	ab049ec Browse files » stm32mp1: use %u in NOTICE message for board info ... The board information values, read in an OTP are never negative, %u is then used instead of %d. Change-Id: I3bc22401fb4d54666ddf56411f75b79aca738492 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 13 Oct 2020
	ade9ce0 Browse files » stm32mp1: get peripheral base address from a define ... Retrieve peripheral base address from a define instead of parsing the device tree. The goal is to improve execution time. Signed-off-by: Pascal Paillet <p.paillet@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2588c53ad3d4abcc3d7fe156458434a7940dd72b Yann Gautier committed on 13 Oct 2020
	f964f5c Browse files » stm32mp1: add finished good variant in board identifier ... Update the board info with the new coding including the finished good variant: Board: MBxxxx Var<CPN>.<FG> Rev.<Rev>-<BOM> The OTP 59 coding is: bit [31:16] (hex) => MBxxxx bit [15:12] (dec) => Variant CPN (1....15) bit [11:8] (dec) => Revision board (index with A = 1, Z = 26) bit [7:4] (dec) => Variant FG : finished good (NEW) bit [3:0] (dec) => BOM (01, .... 255) Change-Id: I4fbc0c84596419d1bc30d166311444ece1d9123f Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Patrick Delaunay authored on 8 Jan 2020 Yann Gautier committed on 13 Oct 2020
	d75a340 Browse files » stm32mp1: add asserts in get_cpu_package() and get_part_number() ... Change-Id: I2b702698d6be93da5ac86da1cbc98b3838315a5a Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Nicolas Le Bayon authored on 23 Sep 2019 Yann Gautier committed on 13 Oct 2020
	8ccf495 Browse files » stm32mp1: add support for new SoC profiles ... Update to support new part numbers. Add new STM32 MPUs Part = STM32MP151F, STM32MP153F, STM32MP157F, STM32MP151D, STM32MP153D, STM32MP157D The STM32MP1 series is available in 3 different lines which are pin-to-pin compatible: - STM32MP157: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz, 3D GPU, DSI display interface and CAN FD - STM32MP153: Dual Cortex-A7 cores, Cortex-M4 core @ 209 MHz and CAN FD - STM32MP151: Single Cortex-A7 core, Cortex-M4 core @ 209 MHz Each line comes with a security option (cryptography & secure boot) & a Cortex-A frequency option : - A Basic + Cortex-A7 @ 650 MHz - C Secure Boot + HW Crypto + Cortex-A7 @ 650 MHz - D Basic + Cortex-A7 @ 800 MHz - F Secure Boot + HW Crypto + Cortex-A7 @ 800 MHz Remove useless variable in stm32mp_is_single_core(). Change-Id: Id30c836af986c6340c91efa8a7ae9480a2827089 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Lionel Debieve authored on 17 May 2019 Yann Gautier committed on 13 Oct 2020
	ffb3f27 Browse files » stm32mp1: support of STM32MP15x Rev.Z ... Add a new revision of STM32MP15x CPU (Rev.Z). Change-Id: I227dd6d9b3fcc43270015cfb21f60aeb0a8ab658 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Lionel Debieve authored on 25 Jun 2019 Yann Gautier committed on 13 Oct 2020