2019-09-10 |
plat: xilinx: zynqmp: Initialize IPI table from zynqmp_config_setup()
...
Common ipi_table needs to be initialized before using any
IPI command (i.e send/receive). Move zynqmp ipi config table
initialization from sip_svc_setup() to zynqmp_config_setup().
Change-Id: Ic8aaa0728a43936cd4c6e1ed590e01ba8f0fbf5b
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Jolly Shah
committed
on 10 Sep 2019
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2019-01-09 |
plat: xilinx: zynqmp: Move zynqmp_private.h to include directory
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Move zynqmp_private.h to platform specific include directory.
Also, rename it to plat_private.h instead of having platform
name. So, it can be used to common source files which needs
platform specific data.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Reviewed-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Jolly Shah
committed
on 9 Jan 2019
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2019-01-04 |
Sanitise includes across codebase
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Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH}
- include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for
includes isn't a good idea. It defeats one of the advantages of having
folders and it introduces problems that are sometimes subtle (because
you may not know the header you are actually including if there are two
of them).
For example, this patch had to be created because two headers were
called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform
to avoid collision."). More recently, this patch has had similar
problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and
source files to logical locations"). At that time, there weren't too
many headers so it wasn't a real issue. However, time has shown that
this creates problems.
Platforms that want to preserve the way they include headers may add the
removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Antonio Nino Diaz
committed
on 4 Jan 2019
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2018-09-04 |
zynqmp: Remove emulation platform support
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This patch removes support for emulation platforms
EP108 and Veloce.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 4 Sep 2018
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2018-06-21 |
plat: xilinx: zynqmp: Get chipid from registers for BL32
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This patch reads the chipid registers directly instead of making
pm call when running at BL32. User should ensure that these registers
should always be accessed from APU in their system configuration.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 21 Jun 2018
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2018-05-17 |
zynqmp: Fix EG/EV detection logic
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The vcu disable bit in efuse ipdisable register is valid
only if PL powered up so, consider PL powerup status for
determing EG/EV part. If PL is not powered up, display
EG/EV as a part of string. The PL powerup status will
be filled by pmufw based on PL PROGB status in the
9th bit of version field.This patch also used IPI
to get this info from pmufw instead of directly accessing
the registers. Accessing this info from pmufw using
IPI fixes the issue of PMUFW access denied error for
reading IPDISABLE register.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Siva Durga Prasad Paladugu
authored
on 5 Mar 2018
Siva Durga Prasad Paladugu
committed
on 17 May 2018
|
xilinx: zynqmp: Remove PMU Firmware checks
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Xilinx now requires the PMU FW when using ATF, so it doesn't make sense
to maintain checks for the PMU FW in ATF. This also means that cases
where ATF came up before the PMU FW (such as on QEMU) ATF will now hang
waiting for the PMU FW instead of aborting.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 17 May 2018
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plat: zynqmp: Add support for CG/EG/EV device detection
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Read ipdisable reg which needs to be used for cg/eg/ev device detection.
ATF runs in EL3 that's why this read can be done directly.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu
committed
on 17 May 2018
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aarch64: zynqmp: Add new Ids for RFSoC
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Add new id codes for RFSoC's.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
authored
on 6 Jun 2017
Siva Durga Prasad Paladugu
committed
on 17 May 2018
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xilinx: zynqmp: Read bootmode register using PM API
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Read boot mode register using pm_mmio_read if pmu is
present otherwise access it directly using mmio_read_32().
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
authored
on 20 Feb 2017
Siva Durga Prasad Paladugu
committed
on 17 May 2018
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2018-03-26 |
plat: fix switch statements to comply with MISRA rules
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Ensure (where possible) that switch statements in plat comply with MISRA
rules 16.1 - 16.7.
Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f
Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
Jonathan Wright
committed
on 26 Mar 2018
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2017-05-03 |
Use SPDX license identifiers
...
To make software license auditing simpler, use SPDX[0] license
identifiers instead of duplicating the license text in every file.
NOTE: Files that have been imported by FreeBSD have not been modified.
[0]: https://spdx.org/
Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a
Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
dp-arm
committed
on 3 May 2017
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2016-11-16 |
zynqmp: pm: Plumb get_chipid through FW interface
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Use the PMUFW get_chipid call to obtain IDCODE and version register.
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 16 Nov 2016
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zynqmp: Do not alter system counter
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On ZynqMP the FSBL will configure the system counter. Hence, remove the
initialization of the system counter with hardcoded values from the ATF
and use the setup provided by the bootloader.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann
committed
on 16 Nov 2016
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zynqmp: Read silicon ID register only once
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The silicon ID does not change at runtime. Skip the IO access if the
ID has been read before.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann
committed
on 16 Nov 2016
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2016-09-13 |
zynqmp: Add support to provide silicon id through SMC
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Add support to provide silicon id to non-secure
software through SMC.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
[ sb
Move zynqmp_get_silicon_id outside of compile guards to avoid build
errors.
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu
authored
on 24 Aug 2016
Soren Brinkmann
committed
on 13 Sep 2016
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zynqmp: Add support for generic_delay_timer
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Initialize the generic_delay_timer in the zynqmp port.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 13 Sep 2016
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2016-06-15 |
Merge pull request #650 from Xilinx/zynqmp-updates
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Zynqmp updates
danh-arm
authored
on 15 Jun 2016
GitHub
committed
on 15 Jun 2016
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2016-05-25 |
zynqmp: Ignore the revision field of the IDCODE
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The revision field may change between silicon revisions without changing
the mapping to a part. This avoids errors like:
ERROR: Incorrect XILINX IDCODE 0x14738093, maskid 0x4600093
NOTICE: ATF running on XCZUUNKN/EP108 v3/RTL5.1 at 0xfffe5000
on parts with a newer revision.
Reported-by: Love Kumar <love.kumar@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Love Kumar <love.kumar@xilinx.com>
Soren Brinkmann
committed
on 25 May 2016
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2016-05-20 |
Implement plat_get_syscnt_freq2 on platforms
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Replaced plat_get_syscnt_freq by plat_get_syscnt_freq2 on all
upstream platforms.
Change-Id: I3248f3f65a16dc5e9720012a05c35b9e3ba6abbe
Antonio Nino Diaz
committed
on 20 May 2016
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2016-04-25 |
zynqmp: Introduce zynqmp_get_bootmode
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Provide a function to retrieve the bootmode.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann
committed
on 25 Apr 2016
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zynqmp: Remove bogus comment
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Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann
committed
on 25 Apr 2016
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2016-04-21 |
Move `plat_get_syscnt_freq()` to arm_common.c
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This patch moves the definition for `plat_get_syscnt_freq()`
from arm_bl31_setup.c to arm_common.c. This could be useful
in case a delay timer needs to be installed based on the
generic timer in other BLs.
This patch also modifies the return type for this function
from `uint64_t` to `unsigned long long` within ARM and other
platform files.
Change-Id: Iccdfa811948e660d4fdcaae60ad1d700e4eda80d
Yatharth Kochar
committed
on 21 Apr 2016
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2016-04-18 |
zynqmp: Remove unused/redundant #includes
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Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann
committed
on 18 Apr 2016
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2016-04-06 |
Add support for Xilinx Zynq UltraScale+ MPSOC
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The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 6 Apr 2016
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