2016-09-08 |
rockchip: fix the scu idle for rk3399
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As rk3399 reported the d8/octane scores drop 10% with cpu idle.
The root cause is thc cpu cluster enter the slow mode.
We don't need switch the clock to 24MHz if cpu cluster enter the
retention mode. In order to improve performance, it just needs for
cluster enter powering off mode.
Also, we shouldn't do anything for hlvl if the system is off.
Change-Id: I2a02962a01343abd0cba47ed63192c1cdf88b119
Tony Xie
authored
on 2 Sep 2016
Caesar Wang
committed
on 8 Sep 2016
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2016-08-25 |
rockchip: handle some interrupt before enter power mode for rk3399
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For the PMU design, we don't expect to get the interrupts before enter
the power mode. Since that will cause the confusion for the state
machine in the power mode.
Change-Id: Id8dee79ae617a66271b5caf92caf35f520f45099
Caesar Wang
committed
on 25 Aug 2016
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rockchip: remove the unused code for rk3399
...
Change-Id: I986d64df9dc62354d50ccea0468b90f090a44160
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Caesar Wang
committed
on 25 Aug 2016
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rockchip: on rk3399 enable Schmitt trigger on 32 kHz clock
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If we don't enable the Schmitt trigger on the 32 kHz clock then systems
won't always resume from suspend properly. Presumably anything else in
the system that relies on the 32 kHz clock also will have problems
without the Schmitt trigger enabled.
Enable it always since having the 32 kHz clock on GPIO0_A0 isn't
exactly an optional feature, so all boards using rk3399 will need this.
Change-Id: Idc18c6cd1adc5be5f60efd9cb805d83d5cd40129
Caesar Wang
committed
on 25 Aug 2016
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2016-08-24 |
rockchip: on rk3399 init the PMU counts at boot; set 24M/32k properly
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In a previous change we mistakenly thought that PMU_24M_EN_CFG directly
controlled whether the PMU counts ran off the 32k vs. 24M clock.
Apparently that's not true. Real logic is now documented in code.
Also in the previous change we mistaknely though that PMU_24M_EN_CFG was
normally supposed to be 1 and we should "restore" it at resume time.
This is a terrible idea and made the system totally unreliable after
resume. Apparently PMU_24M_EN_CFG should always be 0 with all the
current code and settings.
Let's fix the above two problems. While we're changing all of this,
let's also:
1. Init at boot time. Many of these counts are used when the system is
running normally. We want the behavior at boot to match the behavior
after suspend/resume.
2. Init CPU counts to be 1 us. Although old code was trying to set this
to 1 ms (1000x slower) at suspend/resume time, we've been testing the
kernel with 1 us for a long time now. That's because the kernel (at
boot time) set these values to 24. Let's keep at 24 until we know
that's wrong.
3. Init GPU counts to be 1 us. Old code wasn't touching the GPU, but as
documented in comments it makes sense to init here. Do it.
4. Document the crap out of this code, since the SoC's behavior is
confusing and poorly documented in the TRM.
5. Increase some stabilization times to 30 ms (from 3 ms). It's unclear
that a full 30 ms is needed, but let's be safe for now.
This also inits the counts for the GPU.
(Thanks to Doug's patch that come from https://crosreview.com/372381)
Change-Id: Id1bc159a5a99916aeab043895e5c4585c4adab22
Caesar Wang
committed
on 24 Aug 2016
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2016-08-11 |
rockchip: fix the reset-hold release for rk3399 resume
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The pmusgrf reset-hold bits needs to be released, since the
pmusgrf reset-hold bits needs to be held.
Change-Id: Ia1eccc8fba18294f26b4cc07d47bc5e513dd9a1f
Caesar Wang
committed
on 11 Aug 2016
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rockchip: fix the power up/dowm cnt for rk3399
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Sometimes this will cause the long delay for suspend/resume.
Since the 24M OCS will be turned off in power mode.
Also, remove the ERROR_DEPRECATED config define.
Change-Id: I78f21c35912c2250972e551695cdacc7bc4c020a
Caesar Wang
committed
on 11 Aug 2016
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rockchip: update to handle PWMs for rk3399
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This patch updates some things for rk3399, as following:
1) Add the new file to handle the pwm. (e.g. the pwm regulator)
Make sure that good deal with the pwm related things.
Also, remove some pwm setting for pmu.c.
2) Set the plls slow mode and bypass in suspend, and restore them.
Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
Caesar Wang
committed
on 11 Aug 2016
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2016-07-27 |
rockchip: fixes typo and some bugs for suspend/resume tests
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1. Remove the AP_PWROFF in ATF, should configure it in kernel.
2. Save and restore the PWMs pin/regs for suspend/resume.
3. The pmusgrf reset-hold bits needs to be released. since the
pmusgrf reset-hold bits needs to be held.
4. Configure the PMU power up/down cycles about delay 3ms.
5. With the MMIO register block as one big mapping.
6. Fix the build error with psci_entrypoint since PSCI lib updated.
Fixes the commit
9ec78bd ("rockchip: support the suspend/resume for rk3399").
Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
Caesar Wang
committed
on 27 Jul 2016
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2016-07-18 |
rockchip: support the suspend/resume for rk3399
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1.Fixes the suspend/resume some bugs.
2.Add the power domain for saving power consumption.
3.Add cpu clusters suspend for rk3399 SoCs
Change-Id: Id602779016b41d6281f4ba40a20229d909b28e46
Tony Xie
authored
on 15 Jul 2016
Caesar Wang
committed
on 18 Jul 2016
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2016-05-26 |
rockchip: support system off function for rk3399
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if define power off gpio, BL31 will do system power off through
gpio control.
Caesar Wang
committed
on 26 May 2016
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rockchip: support reset SoC through gpio for rk3399
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If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.
Caesar Wang
committed
on 26 May 2016
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2016-05-05 |
Rockchip: Add some debug assertions in the PMU driver
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This patch adds some debug assertions ensuring that array indices
are within the bounds of the array.
Change-Id: I96ee81d14834c1e92cdfb7e60b49995cdacfd93a
Sandrine Bailleux
committed
on 5 May 2016
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2016-05-04 |
rockchip: support the suspend/resume for rk3399
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This patch adds to support the suspend/resume for rk3399 SoCs.
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Caesar Wang
committed
on 4 May 2016
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2016-04-04 |
Support for Rockchip's family SoCs
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This patch adds to support the RK3368 and RK3399 SoCs.
RK3368/RK3399 is one of the Rockchip family SoCs, which is an
multi-cores ARM SoCs.
This patch adds support to boot the Trusted Firmware on RK3368/RK3399
SoCs, and adds support to boot secondary CPUs, enter/exit core
power states for all CPUs in the slow/fast clusters.
This is the initial version for rockchip SoCs.(RK3368/RK3399 and next SoCs)
* Support arm gicv2 & gicv3.
* Boot up multi-cores CPU.
* Add generic CPU helper functions.
* Support suspend/resume.
* Add system_off & system_reset implementation.
* Add delay timer platform implementation.
* Support the new porting interface for the PSCI implementation.
Change-Id: I704bb3532d65e8c70dbd99b512c5e6e440ea6f43
Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
Tony Xie
authored
on 15 Jan 2016
Caesar Wang
committed
on 4 Apr 2016
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