Merge pull request #1623 from MISL-EBU-System-SW/a3700-support ...

Add support for Armada 3700 and COMPHY porting layer

Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2 ...

Allwinner/pmic v2

meson: console: Add missing define to fix build ...

It isn't possible to build this driver without adding this define.

Change-Id: Iba2ced411cd8ce438787871fa01b414d32b9aa42
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

meson: console: Introduce console driver ...

It has only been tested with a system clock of 24 MHz.

It has only been implemented for the multi console API.

Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1640 from soby-mathew/sm/fin_con_reg ...

Multi-console: Deprecate the `finish_console_register` macro

tzc: Fix MISRA defects ...

The definitions FAIL_CONTROL_*_SHIFT were incorrect, they have been
fixed.

The types tzc_region_attributes_t and tzc_action_t have been removed and
replaced by unsigned int because it is not allowed to do logical
operations on enums.

Also, fix some address definitions in arm_def.h.

Change-Id: Id37941d76883f9fe5045a5f0a4224c133c504d8b
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

drivers: marvell Add support for Armada-37xx UART ...

Introduce driver for Marvell Armada-37xx UART console

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

drivers: marvell Add Armada-37xx COMPHY driver ...

Add support for Marvell Armada-3700 COMPHY driver

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

allwinner: Add RSB driver ...

The "Reduced Serial Bus" is an Allwinner specific bus, bearing many
similarities with I2C. It sports a much higher bus frequency, though,
(typically 3 MHz) and requires much less handholding for the typical
task of manipulating slave registers (fire-and-forget).
On most A64 boards this bus is used to connect the PMIC to the SoC.

This driver provides basic primitives to read and write slave registers,
it will be later used by the PMIC code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>

Multi-console: Deprecate the `finish_console_register` macro ...

The `finish_console_register` macro is used by the multi console
framework to register the `console_t` driver callbacks. It relied
on weak references to the `ldr` instruction to populate 0 to the
callback in case the driver has not defined the appropriate
function. Use of `ldr` instruction to load absolute address to a
reference makes the binary position dependant. These instructions
should be replaced with adrp/adr instruction for position independant
executable(PIE). But adrp/adr instructions don't work well with weak
references as described in GNU ld bugzilla issue 22589.

This patch defines a new version of `finish_console_register` macro
which can spcify which driver callbacks are valid and deprecates the
old one. If any of the argument is not specified, then the macro
populates 0 for that callback. Hence the functionality of the previous
deprecated macro is preserved. The USE_FINISH_CONSOLE_REG_2 define
is used to select the new variant of the macro and will be removed
once the deprecated variant is removed.

All the upstream console drivers have been migrated to use the new
macro in this patch.

NOTE: Platforms be aware that the new variant of the
`finish_console_register` should be used and the old variant is
deprecated.

Change-Id: Ia6a67aaf2aa3ba93932992d683587bbd0ad25259
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

Merge pull request #1632 from Yann-lms/stm32mp1_mmc ...

Add MMC support for STM32MP1

mvebu: cp110: introduce COMPHY porting layer ...

Some of COMPHY parameters depends on the hw connection between the SoC
and the PHY, which can vary on different boards e.g. due to different
wires length. Define the "porting layer" with some defaults
parameters. It ease updating static values which needs to be updated due
to board differences, which are now grouped in one place.

Example porting layer for a8k-db is under:
plat/marvell/a8k/a80x0/board/phy-porting-layer.h

If for some boards parameters are not defined (missing
phy-porting-layer.h), the default values are used
(drivers/marvell/comphy/phy-default-porting-layer.h)
and the following compilation warning is show:
"Using default comphy params - you may need to suit them to your board".

The common COMPHY driver code is extracted in order to be shared with
future COMPHY driver for A3700 SoC platforms

Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

rcar_gen3: drivers: watchdog ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: serial controller interface ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: spi multio bus controller ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: rom api ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: power controller ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: console ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: io [emmc/mem] ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: i2c dvfs ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: emmc ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: dma ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: micro delay generator ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: cpld ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: board identification ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: avs [adaptive voltage scaling] ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: authentication ...

Signed-off-by: ldts <jramirez@baylibre.com>

rcar_gen3: drivers: staging ...

- ddr
 - pfc [pin function controller]
 - qos [bandwidth]

checkpatch.pl is generating too many errors.

rcar-gen3: initial commit for the rcar-gen3 boards ...

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
    Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

Signed-off-by: ldts <jramirez@baylibre.com>

stm32mp1: add an IO to read MMC devices ...

Whereas the GPT table is read with io_block, the binaries to be loaded
(e.g. BL33) cannot use it, as it is not suitable to read them block by
block, or the boot time would be very bad.

Signed-off-by: Yann Gautier <yann.gautier@st.com>