LuminaSensum/arm-trusted-firmware

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LuminaSensum / arm-trusted-firmware

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2017-11-29	ef69e1e Browse files » AMU: Implement support for aarch32 ... The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: Ifc7532ef836f83e629f2a146739ab61e75c4abc8 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 29 Nov 2017
	380559c Browse files » AMU: Implement support for aarch64 ... The `ENABLE_AMU` build option can be used to enable the architecturally defined AMU counters. At present, there is no support for the auxiliary counter group. Change-Id: I7ea0c0a00327f463199d1b0a481f01dadb09d312 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 29 Nov 2017
	0319a97 Browse files » Implement support for the Activity Monitor Unit on Cortex A75 ... The Cortex A75 has 5 AMU counters. The first three counters are fixed and the remaining two are programmable. A new build option is introduced, `ENABLE_AMU`. When set, the fixed counters will be enabled for use by lower ELs. The programmable counters are currently disabled. Change-Id: I4bd5208799bb9ed7d2596e8b0bfc87abbbe18740 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 29 Nov 2017
2017-11-23	Unverified 71f8a6a Browse files » Merge pull request #1145 from etienne-lms/rfc-armv7-2 ... Support ARMv7 architectures davidcunado-arm authored on 23 Nov 2017 GitHub committed on 23 Nov 2017
2017-11-23	Unverified 1c64838 Browse files » Merge pull request #1164 from robertovargas-arm/psci-affinity ... Flush the affinity data in psci_affinity_info davidcunado-arm authored on 23 Nov 2017 GitHub committed on 23 Nov 2017
2017-11-22	Unverified fe964ec Browse files » Merge pull request #1163 from antonio-nino-diaz-arm/an/parange ... Add ARMv8.2 ID_AA64MMFR0_EL1.PARange value davidcunado-arm authored on 22 Nov 2017 GitHub committed on 22 Nov 2017
2017-11-20	8fd307f Browse files » Flush the affinity data in psci_affinity_info ... There is an edge case where the cache maintaince done in psci_do_cpu_off may not seen by some cores. This case is handled in psci_cpu_on_start but it hasn't handled in psci_affinity_info. Change-Id: I4d64f3d1ca9528e364aea8d04e2d254f201e1702 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com> Roberto Vargas committed on 20 Nov 2017
	281a08c Browse files » Refactor Statistical Profiling Extensions implementation ... Factor out SPE operations in a separate file. Use the publish subscribe framework to drain the SPE buffers before entering secure world. Additionally, enable SPE before entering normal world. A side effect of this change is that the profiling buffers are now only drained when a transition from normal world to secure world happens. Previously they were drained also on return from secure world, which is unnecessary as SPE is not supported in S-EL1. Change-Id: I17582c689b4b525770dbb6db098b3a0b5777b70a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 20 Nov 2017
	0fd0f22 Browse files » Factor out extension enabling to a separate function ... Factor out extension enabling to a separate function that is called before exiting from EL3 for first entry into Non-secure world. Change-Id: Ic21401ebba531134d08643c0a1ca9de0fc590a1b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 20 Nov 2017
2017-11-17	6504b2c Browse files » Add ARMv8.2 ID_AA64MMFR0_EL1.PARange value ... If an implementation of ARMv8.2 includes ARMv8.2-LPA, the value 0b0110 is permitted in ID_AA64MMFR0_EL1.PARange, which means that the Physical Address range supported is 52 bits (4 PiB). It is a reserved value otherwise. Change-Id: Ie0147218e9650aa09f0034a9ee03c1cca8db908a Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 17 Nov 2017
2017-11-15	91089f3 Browse files » Move FPEXC32_EL2 to FP Context ... The FPEXC32_EL2 register controls SIMD and FP functionality when the lower ELs are executing in AArch32 mode. It is architecturally mapped to AArch32 system register FPEXC. This patch removes FPEXC32_EL2 register from the System Register context and adds it to the floating-point context. EL3 only saves / restores the floating-point context if the build option CTX_INCLUDE_FPREGS is set to 1. The rationale for this change is that if the Secure world is using FP functionality and EL3 is not managing the FP context, then the Secure world will save / restore the appropriate FP registers. NOTE - this is a break in behaviour in the unlikely case that CTX_INCLUDE_FPREGS is set to 0 and the platform contains an AArch32 Secure Payload that modifies FPEXC, but does not save and restore this register Change-Id: Iab80abcbfe302752d52b323b4abcc334b585c184 Signed-off-by: David Cunado <david.cunado@arm.com> David Cunado committed on 15 Nov 2017
2017-11-09	Unverified 9500d5a Browse files » Merge pull request #1148 from antonio-nino-diaz-arm/an/spm ... Introduce Secure Partition Manager davidcunado-arm authored on 9 Nov 2017 GitHub committed on 9 Nov 2017
2017-11-08	ad02a75 Browse files » xlat: Make function to calculate TCR PA bits public ... This function can be useful to setup TCR_ELx by callers that don't use the translation tables library to setup the system registers related to them. By making it common, it can be reused whenever it is needed without duplicating code. Change-Id: Ibfada9e846d2a6cd113b1925ac911bb27327d375 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 8 Nov 2017
	1d79153 Browse files » ARMv7: division support for missing __aeabi_*divmod ... ARMv7-A architectures that do not support the Virtualization extensions do not support instructions for the 32bit division. This change provides a software implementation for 32bit division. The division implementation is dumped from the OP-TEE project http://github.com/OP-TEE/optee_os. The code was slightly modified to pass trusted firmware checkpatch requirements and copyright is given to the ARM trusted firmware initiative and its contributors. Change-Id: Idae0c7b80a0d75eac9bd41ae121921d4c5af3fa3 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	86e2683 Browse files » ARMv7 may not support Generic Timer Extension ... If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_GENERIC_TIMER to enable generic timer support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	51b992e Browse files » ARMv7 may not support large page addressing ... ARCH_SUPPORTS_LARGE_PAGE_ADDRESSING allows build environment to handle specific case when target ARMv7 core only supports 32bit MMU descriptor mode. If ARMv7 based platform does not set ARM_CORTEX_Ax=yes, platform shall define ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING to enable large page addressing support. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	1ca8d02 Browse files » ARMv7: introduce Cortex-A12 ... Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	778e411 Browse files » ARMv7: introduce Cortex-A17 ... Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	6ff43c2 Browse files » ARMv7: introduce Cortex-A7 ... Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	d56a846 Browse files » ARMv7: introduce Cortex-A5 ... Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	e3148c2 Browse files » ARMv7: introduce Cortex-A9 ... As Cortex-A9 needs to manually enable program flow prediction, do not reset SCTLR[Z] at entry. Platform should enable it only once MMU is enabled. Change-Id: I34e1ee2da73221903f7767f23bc6fc10ad01e3de Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	10922e7 Browse files » ARMv7: introduce Cortex-A15 ... Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
	0147bef Browse files » ARMv7 does not support STL instruction ... Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Etienne Carriere committed on 8 Nov 2017
2017-11-03	bfc87a8 Browse files » Fix PSCI STAT time stamp collection ... This patch includes various fixes for PSCI STAT functionality relating to timestamp collection: 1. The PSCI stat accounting for retention states for higher level power domains were done outside the locks which could lead to spurious values in some race conditions. This is moved inside the locks. Also, the call to start the stat accounting was redundant which is now removed. 2. The timestamp wrap-around case when calculating residency did not cater for AArch32. This is now fixed. 3. In the warm boot path, `plat_psci_stat_accounting_stop()` was getting invoked prior to population of target power states. This is now corrected. Change-Id: I851526455304fb74ff0a724f4d5318cd89e19589 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Soby Mathew committed on 3 Nov 2017
2017-10-31	17b4c0d Browse files » aarch64: Add PubSub events to capture security state transitions ... Add events that trigger before entry to normal/secure world. The events trigger after the normal/secure context has been restored. Similarly add events that trigger after leaving normal/secure world. The events trigger after the normal/secure context has been saved. Change-Id: I1b48a7ea005d56b1f25e2b5313d77e67d2f02bc5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Dimitris Papastamos committed on 31 Oct 2017
2017-10-23	bd0c347 Browse files » PSCI: Publish CPU ON event ... This allows other EL3 components to subscribe to CPU on events. Update Firmware Design guide to list psci_cpu_on_finish as an available event. Change-Id: Ida774afe0f9cdce4021933fcc33a9527ba7aaae2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 23 Oct 2017
2017-10-20	8b9f419 Browse files » Merge pull request #1136 from antonio-nino-diaz-arm/an/xlat-get-set-attr ... Add APIs to get and modify attributes of memory regions davidcunado-arm authored on 20 Oct 2017 GitHub committed on 20 Oct 2017
2017-10-17	ccd0c24 Browse files » Merge pull request #1127 from davidcunado-arm/dc/pmrc_init ... Init and save / restore of PMCR_EL0 / PMCR davidcunado-arm authored on 17 Oct 2017 GitHub committed on 17 Oct 2017
	5d2f87e Browse files » Merge pull request #1126 from robertovargas-arm/psci-v1.1 ... Update PSCI to v1.1 davidcunado-arm authored on 17 Oct 2017 GitHub committed on 17 Oct 2017
	ec0c8fd Browse files » Introduce functions to disable the MMU in EL1 ... The implementation is the same as those used to disable it in EL3. Change-Id: Ibfe7e69034a691fbf57477c5a76a8cdca28f6b26 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Antonio Nino Diaz committed on 17 Oct 2017