2016-02-22 |
Merge pull request #532 from soby-mathew/vk/configure_mmap_macros
...
Rationalise MMU and Page table related constants on ARM platforms
danh-arm
committed
on 22 Feb 2016
|
Rationalise MMU and Page table related constants on ARM platforms
...
`board_arm_def.h` contains multiple definitions of
`PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` that are optimised for
memory usage depending upon the chosen build configuration. To ease
maintenance of these constants, this patch replaces their multiple
definitions with a single set of definitions that will work on all ARM
platforms.
Platforms can override the defaults with optimal values by enabling the
`ARM_BOARD_OPTIMISE_MMAP` build option. An example has been provided in
the Juno ADP port.
Additionally, `PLAT_ARM_MMAP_ENTRIES` is increased by one to accomodate
future ARM platforms.
Change-Id: I5ba6490fdd1e118cc9cc2d988ad7e9c38492b6f0
Vikram Kanigiri
authored
on 20 Jan 2016
Soby Mathew
committed
on 22 Feb 2016
|
Merge pull request #518 from hzhuang1/pl061_gpio_v5
...
Pl061 gpio v5
danh-arm
committed
on 22 Feb 2016
|
2016-02-19 |
Merge pull request #531 from soby-mathew/sm/multicluster_fvp
...
Allow multi cluster topology definitions for ARM platforms
danh-arm
committed
on 19 Feb 2016
|
Allow multi cluster topology definitions for ARM platforms
...
The common topology description helper funtions and macros for
ARM Standard platforms assumed a dual cluster system. This is not
flexible enough to scale to multi cluster platforms. This patch does
the following changes for more flexibility in defining topology:
1. The `plat_get_power_domain_tree_desc()` definition is moved from
`arm_topology.c` to platform specific files, that is `fvp_topology.c`
and `juno_topology.c`. Similarly the common definition of the porting
macro `PLATFORM_CORE_COUNT` in `arm_def.h` is moved to platform
specific `platform_def.h` header.
2. The ARM common layer porting macros which were dual cluster specific
are now removed and a new macro PLAT_ARM_CLUSTER_COUNT is introduced
which must be defined by each ARM standard platform.
3. A new mandatory ARM common layer porting API
`plat_arm_get_cluster_core_count()` is introduced to enable the common
implementation of `arm_check_mpidr()` to validate MPIDR.
4. For the FVP platforms, a new build option `FVP_NUM_CLUSTERS` has been
introduced which allows the user to specify the cluster count to be
used to build the topology tree within Trusted Firmare. This enables
Trusted Firmware to be built for multi cluster FVP models.
Change-Id: Ie7a2e38e5661fe2fdb2c8fdf5641d2b2614c2b6b
Soby Mathew
committed
on 19 Feb 2016
|
2016-02-18 |
Merge pull request #529 from sandrine-bailleux/sb/a57-sw-optim-ref
...
Cortex-A57: Add link to software optimization guide
danh-arm
committed
on 18 Feb 2016
|
Merge pull request #528 from antonio-nino-diaz-arm/an/user_guide
...
Move up FVP versions in the user guide
danh-arm
committed
on 18 Feb 2016
|
Merge pull request #526 from antonio-nino-diaz-arm/an/missing_doc
...
Add missing build options to the User Guide
danh-arm
committed
on 18 Feb 2016
|
Merge pull request #524 from jcastillo-arm/jc/tf-issues/319
...
Improve memory layout documentation
danh-arm
committed
on 18 Feb 2016
|
Cortex-A57: Add link to software optimization guide
...
This patch adds a link to the Cortex-A57 Software Optimization Guide
in the ARM CPU Specific Build Macros document to justify the default
value of the A57_DISABLE_NON_TEMPORAL_HINT build flag.
Change-Id: I9779e42a4bb118442b2b64717ce143314ec9dd16
Sandrine Bailleux
committed
on 18 Feb 2016
|
2016-02-17 |
Add missing build options to the User Guide
...
The folowing build options were missing from the User Guide and have been
documented:
- CTX_INCLUDE_FPREGS
- DISABLE_PEDANTIC
- BUILD_STRING
- VERSION_STRING
- BUILD_MESSAGE_TIMESTAMP
Change-Id: I6a9c39ff52cad8ff04deff3ac197af84d437b8b7
Antonio Nino Diaz
committed
on 17 Feb 2016
|
2016-02-16 |
Make SCP_BL2(U) image loading configurable on CSS platforms
...
Current code mandates loading of SCP_BL2/SCP_BL2U images for all
CSS platforms. On future ARM CSS platforms, the Application
Processor (AP) might not need to load these images. So, these
items can be removed from the FIP on those platforms.
BL2 tries to load SCP_BL2/SCP_BL2U images if their base
addresses are defined causing boot error if the images are not
found in FIP.
This change adds a make flag `CSS_LOAD_SCP_IMAGES` which if set
to `1` does:
1. Adds SCP_BL2, SCP_BL2U images to FIP.
2. Defines the base addresses of these images so that AP loads
them.
And vice-versa if it is set to `0`. The default value is set to
`1`.
Change-Id: I5abfe22d5dc1e9d80d7809acefc87b42a462204a
Vikram Kanigiri
committed
on 16 Feb 2016
|
2016-02-12 |
Document: add PLAT_PL061_MAX_GPIOS define
...
ARM PL061 GPIO driver requires the "PLAT_PL061_MAX_GPIOS" definition.
By default, it's defined to 32 in PL061 GPIO driver. If user wants
more PL061 controllers in platform, user should define the build
flag in platform.mk instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Haojian Zhuang
committed
on 12 Feb 2016
|
2016-02-08 |
Disable non-temporal hint on Cortex-A53/57
...
The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.
This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.
The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.
Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1
Sandrine Bailleux
committed
on 8 Feb 2016
|
2016-02-05 |
Move up FVP versions in the user guide
...
Move up to Base FVP version 7.2 (build 0.8/7202) and Foundation FVP version
9.5 (build 9.5.41) in the user guide.
Change-Id: Ie9900596216808cadf45f042eec639d906e497b2
Antonio Nino Diaz
committed
on 5 Feb 2016
|
2016-02-01 |
Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap
...
Porting Guide: Clarify identity-mapping requirement
danh-arm
committed
on 1 Feb 2016
|
Merge pull request #503 from sandrine-bailleux/sb/clarify-doc-el3-payloads
...
Clarify EL3 payload documentation
danh-arm
committed
on 1 Feb 2016
|
Merge pull request #501 from jcastillo-arm/jc/tf-issues/300
...
Disable PL011 UART before configuring it
danh-arm
committed
on 1 Feb 2016
|
Improve memory layout documentation
...
This patch adds a brief explanation of the top/bottom load approach
to the Firmware Design guide and how Trusted Firmware keeps track of
the free memory at boot time. This will help platform developers to
avoid unexpected results in the memory layout.
Fixes ARM-software/tf-issues#319
Change-Id: I04be7e24c1f3b54d28cac29701c24bf51a5c00ad
Juan Castillo
committed
on 1 Feb 2016
|
2016-01-29 |
Porting Guide: Clarify identity-mapping requirement
...
The memory translation library in Trusted Firmware supports
non-identity mappings for Physical to Virtual addresses since commit
f984ce84ba. However, the porting guide hasn't been updated
accordingly and still mandates the platform ports to use
identity-mapped page tables for all addresses.
This patch removes this out-dated information from the Porting Guide
and clarifies in which circumstances non-identity mapping may safely
be used.
Fixes ARM-software/tf-issues#258
Change-Id: I84dab9f3cabfc43794951b1828bfecb13049f706
Sandrine Bailleux
committed
on 29 Jan 2016
|
Clarify EL3 payload documentation
...
This patch reworks the section about booting an EL3 payload in the
User Guide:
- Centralize all EL3 payload related information in the same
section.
- Mention the possibility to program the EL3 payload in flash memory
and execute it in place.
- Provide model parameters for both the Base and Foundation FVPs.
- Provide some guidance to boot an EL3 payload on Juno.
Change-Id: I975c8de6b9b54ff4de01a1154cba63271d709912
Sandrine Bailleux
committed
on 29 Jan 2016
|
2016-01-25 |
Merge pull request #495 from jcastillo-arm/jc/tf-issues/170
...
ARM plat: add build option to unlock access to non-secure timer
danh-arm
committed
on 25 Jan 2016
|
2016-01-21 |
Disable PL011 UART before configuring it
...
The PL011 TRM (ARM DDI 0183G) specifies that the UART must be
disabled before any of the control registers are programmed. The
PL011 driver included in TF does not disable the UART, so the
initialization in BL2 and BL31 is violating this requirement
(and potentially in BL1 if the UART is enabled after reset).
This patch modifies the initialization function in the PL011
console driver to disable the UART before programming the
control registers.
Register clobber list and documentation updated.
Fixes ARM-software/tf-issues#300
Change-Id: I839b2d681d48b03f821ac53663a6a78e8b30a1a1
Juan Castillo
committed
on 21 Jan 2016
|
2016-01-20 |
ARM plat: add build option to unlock access to non-secure timer
...
Currently, Trusted Firmware on ARM platforms unlocks access to the
timer frame registers that will be used by the Non-Secure world. This
unlock operation should be done by the Non-Secure software itself,
instead of relying on secure firmware settings.
This patch adds a new ARM specific build option 'ARM_CONFIG_CNTACR'
to unlock access to the timer frame by setting the corresponding
bits in the CNTACR<N> register. The frame id <N> is defined by
'PLAT_ARM_NSTIMER_FRAME_ID'. Default value is true (unlock timer
access).
Documentation updated accordingly.
Fixes ARM-software/tf-issues#170
Change-Id: Id9d606efd781e43bc581868cd2e5f9c8905bdbf6
Juan Castillo
committed
on 20 Jan 2016
|
2016-01-18 |
Merge pull request #493 from yupluo01/yp/tf-issue-fix-doc-links
...
Update doc links in the porting guide
danh-arm
committed
on 18 Jan 2016
|
2016-01-17 |
Update doc links in the porting guide
...
GIC v2 and v3 specification references in the porting guide
should refer to publically visible links, not ARM internal links.
Change-Id: Ib47c8adda6a03581f23bcaed72d71c08c7dd9fb1
Signed-off-by: Yuping Luo <yuping.luo@arm.com>
Yuping Luo
committed
on 17 Jan 2016
|
2016-01-15 |
Merge pull request #489 from sandrine-bailleux/sb/fix-mailbox-doc
...
Doc: Update out-dated info about Juno's mailbox
danh-arm
committed
on 15 Jan 2016
|
Doc: Update out-dated info about Juno's mailbox
...
Since commit 804040d106, the Juno port has moved from per-CPU mailboxes
to a single shared one. This patch updates an out-dated reference to
the former per-CPU mailboxes mechanism in the Firmware Design.
Change-Id: I355b54156b1ace1b3df4c4416e1e8625211677fc
Sandrine Bailleux
committed
on 15 Jan 2016
|
2016-01-14 |
Remove direct usage of __attribute__((foo))
...
Migrate all direct usage of __attribute__ to usage of their
corresponding macros from cdefs.h.
e.g.:
- __attribute__((unused)) -> __unused
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Soren Brinkmann
committed
on 14 Jan 2016
|
2016-01-13 |
Merge pull request #485 from jcastillo-arm/jc/max_mmap_reg
...
Add 'MAX_MMAP_REGIONS' and 'ADDR_SPACE_SIZE' to the Porting Guide
danh-arm
committed
on 13 Jan 2016
|