LuminaSensum/arm-trusted-firmware

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History for arm-trusted-firmware / plat

2019-11-19	b7f6525 Browse files » Enable -Wshadow always ... Variable shadowing is, according to the C standard, permitted and valid behaviour. However, allowing a local variable to take the same name as a global one can cause confusion and can make refactoring and bug hunting more difficult. This patch moves -Wshadow from WARNING2 into the general warning group so it is always used. It also fixes all warnings that this introduces by simply renaming the local variable to a new name Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e Signed-off-by: Justin Chadwell <justin.chadwell@arm.com> Justin Chadwell authored on 17 Sep 2019 Madhukar Pappireddy committed on 19 Nov 2019
2019-11-19	af1ac83 Browse files » Merge changes from topic "tegra-downstream-092319" into integration ... * changes: Tegra194: remove L2 ECC parity protection setting Tegra194: sip_calls: mark unused parameter as const Tegra194: implement handler to retrieve power domain tree Tegra194: mce: fix function declaration conflicts Tegra194: add macros to read GPU reset status Tegra194: skip notifying MCE in fake system suspend Tegra194: Enable system suspend Sandrine Bailleux authored on 19 Nov 2019 TrustedFirmware Code Review committed on 19 Nov 2019
2019-11-18	896add4 Browse files » Merge changes from topic "lm/improve_memory_layout" into integration ... * changes: DOC: Update ROMLIB page with memory impact info ROMLIB: Optimize memory layout when ROMLIB is used Sandrine Bailleux authored on 18 Nov 2019 TrustedFirmware Code Review committed on 18 Nov 2019
2019-11-18	e7b3908 Browse files » ROMLIB: Optimize memory layout when ROMLIB is used ... ROMLIB extract functions code from BL images to put them inside ROM. This has for effect to reduce the size of the BL images. This patch take this size reduction into consideration to optimize the memory layout of BL2. A new "PLAT_ARM_BL2_ROMLIB_OPTIMIZATION" macro is defined and used to reduce "PLAT_ARM_MAX_BL2_SIZE". This allows to remove the gap between BL1 and BL2 when ROMLIB is used and provides more room for BL31. The current memory gain is 0x6000 for fvp and 0x8000 for juno. Change-Id: I71c2c2c63b57bce5b22a125efaefc486ff3e87be Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 18 Nov 2019
2019-11-13	d191573 Browse files » Tegra194: remove L2 ECC parity protection setting ... This patch removes the code to enable L2 ECC parity protection bit, as Tegra194 does not have any Cortex-A57 CPUs. Change-Id: I4b56595fea2652e8bb8ab4a7ae7567278ecff9af Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com> Harvey Hsieh authored on 23 Nov 2016 Varun Wadekar committed on 13 Nov 2019
	2e446f5 Browse files » Tegra194: sip_calls: mark unused parameter as const ... This patch marks the unused parameter 'cookie', to the plat_sip_handler() function, as const to fix an issue flagged by the MISRA scan. Change-Id: I53fdd2caadf43fef17fbc3a50a18bf7fdbd42d39 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 13 Nov 2019
	42de038 Browse files » Tegra194: implement handler to retrieve power domain tree ... This patch implements the platform handler to return the pointer to the power domain tree. Change-Id: I74ea7002c7a461a028b4a252bbd354256fdc0647 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 13 Nov 2019
	73dad7f Browse files » Tegra194: mce: fix function declaration conflicts ... To fix MISRA defects, remove union in t186 MCE drivers this driver should compatible with that. Change-Id: I09e96a1874dd86626c7e41c92a1484a84e387402 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Anthony Zhou authored on 28 Apr 2017 Varun Wadekar committed on 13 Nov 2019
	2fdd9ae Browse files » Tegra194: add macros to read GPU reset status ... This patch adds macros to check the GPU reset status bit, before resizing the VideoMem region. Change-Id: I4377c1ce1ac6d3bd14c7db83526b99d72bdb41ed Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 13 Nov 2019
	5da8ec5 Browse files » Tegra194: skip notifying MCE in fake system suspend ... - In pre-silicon platforms, MCE might not be ready to support system suspend(SC7) - Thus, in fake system suspend mode, bypass waiting for MCE's acknowledgment to enter system suspend Change-Id: Ia3c010ce080c4283ab1233ba82e3e577adca34f6 Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com> Vignesh Radhakrishnan authored on 10 Apr 2017 Varun Wadekar committed on 13 Nov 2019
	12f06f1 Browse files » Tegra194: Enable system suspend ... This patch does the following: 1. Populate the cstate info corresponding to system suspend and communicate it to the MCE 2. Ask for MCE's acknowledgement for entering system suspend and instruct MCE to get inside system suspend once permitted Change-Id: I51e1910e24a7e61e36ac2d12ce271290e433e506 Signed-off-by: Tejal Kudav <tkudav@nvidia.com> Signed-off-by: Vignesh Radhakrishnan <vigneshr@nvidia.com> Tejal Kudav authored on 14 Feb 2017 Varun Wadekar committed on 13 Nov 2019
	a011942 Browse files » Merge changes from topic "tegra-downstream-092319" into integration ... * changes: Tegra194: add macros for security carveout configuration registers Tegra194: add 'TEGRA_TMRUS_SIZE' macro Tegra194: Fix TEGRA186_SMMU_CTX_SIZE Tegra194: Dont run MCE firmware on Emulation Tegra194: remove GPU, MPCORE and PTC registers from streamid list Tegra194: Support SMC64 encoding for MCE calls Tegra194: Enable MCE driver Tegra194: enable SMMU Tegra194: add support for multiple SMMU devices Tegra194: add SMMU and mc_sid support Tegra194: psci: support for 64-bit TZDRAM base Tegra194: base commit for the platform Revert "Tegra: Add support for fake system suspend" Sandrine Bailleux authored on 13 Nov 2019 TrustedFirmware Code Review committed on 13 Nov 2019
2019-11-12	63b9627 Browse files » Merge "plat/arm: Re-enable PIE when RESET_TO_BL31=1" into integration Paul Beesley authored on 12 Nov 2019 TrustedFirmware Code Review committed on 12 Nov 2019
2019-11-11	6799a37 Browse files » n1sdp: setup multichip gic routing table ... N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link, for now only dual-chip is supported. Whether or not multiple chips are present is dynamically probed by SCP firmware and passed on to TF-A, routing table will be set up only if multiple chips are present. Initialize GIC-600 multichip operation by overriding the default GICR frames with array of GICR frames and setting the chip 0 as routing table owner. Change-Id: Ida35672be4bbf4c517469a5b330548d75e593ff2 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey authored on 14 Oct 2019 Vijayenthiran Subramaniam committed on 11 Nov 2019
2019-11-07	133a5c6 Browse files » plat/arm: Re-enable PIE when RESET_TO_BL31=1 ... Earlier PIE support was enabled for all arm platforms when RESET_TO_BL31=1, but later on it was restricted only to FVP with patch SHA d4580d17 because of n1sdp platform. Now it has been verified that PIE does work for n1sdp platform also, so enabling it again for all arm platforms. Change-Id: I05ad4f1775ef72e7cb578ec9245cde3fbce971a5 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 7 Nov 2019
2019-11-05	74c2124 Browse files » plat/arm/gicv3: add support for probing multiple GIC Redistributor frames ... ARM platform can have a non-contiguous GICR frames. For instance, a multi socket platform can have two or more GIC Redistributor frames which are 4TB apart. Hence it is necessary for the `gicv3_rdistif_probe` function to probe all the GICR frames available in the platform. Introduce `plat_arm_override_gicr_frames` function which platforms can use to override the default gicr_frames which holds the GICR base address of the primary cpu. Change-Id: I1f537b0d871a679cb256092944737f2e55ab866e Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com> Vijayenthiran Subramaniam committed on 5 Nov 2019
2019-10-31	f91a8e4 Browse files » n1sdp: update platform macros for dual-chip setup ... N1SDP supports multichip configuration wherein n1sdp boards are connected over high speed coherent CCIX link for now only dual-chip is supported. A single instance of TF-A runs on master chip which should be aware of slave chip's CPU and memory topology. This patch updates platform macros to include remote chip's information and also ensures that a single version of firmware works for both single and dual-chip setup. Change-Id: I75799fd46dc10527aa99585226099d836c21da70 Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 31 Oct 2019
2019-10-30	34c7af4 Browse files » n1sdp: introduce platform information SDS region ... Platform information structure holds information about platform's DDR size(local/remote) which will be used to zero out the memory before enabling the ECC capability as well as information about multichip setup. Multichip and remote DDR information can only be probed in SCP, SDS region will be used by TF-A to get this information at boot up. This patch introduces a new SDS to store platform information, which is populated dynamically by SCP Firmware.previously used mem_info SDS is also made part of this structure itself. The platform information is also passed to BL33 by copying it to Non- Secure SRAM. Change-Id: I4781dc6a7232c3c0a3219b164d943ce9e3e469ee Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Manish Pandey committed on 30 Oct 2019
2019-10-29	ff835a9 Browse files » ti: k3: common: Add PIE support ... Running TF-A from non-standard location such as DRAM is useful for some SRAM heavy use-cases. Allow the TF-A binary to be executed from an arbitrary memory location. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Icd97926e4d97f37d7cde4a92758a52f57d569111 Andrew F. Davis committed on 29 Oct 2019
2019-10-24	3b2b337 Browse files » Tegra194: add macros for security carveout configuration registers ... This patch adds macros defining the generalised security carveout registers. These macros help us program the TZRAM carveout access and the Video Protect Clear carveout access. Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 24 Oct 2019
	d82f5a3 Browse files » Tegra194: add 'TEGRA_TMRUS_SIZE' macro ... This patch defines the macro for the TEGRA_TMRUS aperture size. Change-Id: I33fb674c6a7be8d02971667e7bf8650b7adc62ef Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 7 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	ddbf946 Browse files » Tegra194: Fix TEGRA186_SMMU_CTX_SIZE ... TEGRA186_SMMU_CTX_SIZE should match the numbe of elements in smmu_ctx_regs, which is defined in smmu_plat_config.h. The current number of elements are 0x490. Change-Id: If0614ea8ef8b6a8f5da1a3279abaf9255eb76420 Signed-off-by: Stefan Kristiansson <stefank@nvidia.com> Stefan Kristiansson authored on 20 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	4fb71ea Browse files » Tegra194: Dont run MCE firmware on Emulation ... Dont run MCE firmware on pre-silicon emulation platforms Change-Id: I2a8d653e46f494621580ca92271a18e62f648859 Signed-off-by: Rohit Khanna <rokhanna@nvidia.com> Rohit Khanna authored on 3 Mar 2017 Varun Wadekar committed on 24 Oct 2019
	e9bb627 Browse files » Tegra194: remove GPU, MPCORE and PTC registers from streamid list ... GPU, MPCORE and PTC clients are changed and not going through SMMU. Removing it from streamid list. Change-Id: I14b450a11f02ad6c1a97e67e487d6d624911d019 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 13 Feb 2017 Varun Wadekar committed on 24 Oct 2019
	7e4ffcd Browse files » Tegra194: Support SMC64 encoding for MCE calls ... This patch uses SMC64 encoding for all MCE SMC calls originating from the linux kernel. Change-Id: Ic4633de5c638566012db033bbaf8c9d9343acdc0 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 24 Oct 2019
	9808032 Browse files » Tegra194: Enable MCE driver ... This patch enable MCE driver for T19x SoC. The MCE driver takes care of the communication with the MCE firmware to achieve: - Cold boot - Warm boot - Core/Cluster/System Power management - Custom MCE requests Change-Id: I75854c0b649a691e9b244d9ed9fc1c19743e3e8d Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 5 Jan 2017 Varun Wadekar committed on 24 Oct 2019
	5660eeb Browse files » Tegra194: enable SMMU ... Enable smmu by setting ENABLE_SMMU_DEVICE to 1. Change-Id: I9135071b257a166fa6082b7fe409bcd315cf6838 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 24 Jan 2017 Varun Wadekar committed on 24 Oct 2019
	0ea8881 Browse files » Tegra194: add support for multiple SMMU devices ... This patch adds support for all three SMMU devices present on the SoC. The following changes have been done: Add SMMU devices to the memory map Update register read and write functions Change-Id: I0007b496d2ae7264f4fa9f605d4b0a15fa747a0f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 24 Jan 2017 Varun Wadekar committed on 24 Oct 2019
	2ac8cb7 Browse files » Tegra194: add SMMU and mc_sid support ... Define mc sid and txn override regs and sec cfgs. Create array for mc sid override regs and sec config that is used to initialize mc. Add smmu ctx regs array to hold register values during suspend. Change-Id: I7b265710a9ec2be7dea050058bce65c614772c78 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 2 Jan 2017 Varun Wadekar committed on 24 Oct 2019
	d11c793 Browse files » Tegra194: psci: support for 64-bit TZDRAM base ... This patch fixes the variable width to store the TZDRAM base address used to resume from System Suspend. Change-Id: I3c18eb844963f39f91b5ac45e3709f3354bcda0c Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 23 Dec 2016 Varun Wadekar committed on 24 Oct 2019