2015-04-27 |
Remove use of PLATFORM_CACHE_LINE_SIZE
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The required platform constant PLATFORM_CACHE_LINE_SIZE is
unnecessary since CACHE_WRITEBACK_GRANULE effectively provides the
same information. CACHE_WRITEBACK_GRANULE is preferred since this
is an architecturally defined term and allows comparison with the
corresponding hardware register value.
Replace all usage of PLATFORM_CACHE_LINE_SIZE with
CACHE_WRITEBACK_GRANULE.
Also, add a runtime assert in BL1 to check that the provided
CACHE_WRITEBACK_GRANULE matches the value provided in CTR_EL0.
Change-Id: If87286be78068424217b9f3689be358356500dcd
Dan Handley
committed
on 27 Apr 2015
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2015-01-28 |
FVP: initialize IO framework in bl2_early_platform_setup()
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This patch moves fvp_io_setup() to bl2_early_platform_setup() in order
to allow BL2 to use the IO framework before bl2_platform_setup().
Change-Id: I75e1a772ab5f9b4727f6727822a2527c30f3c63d
Juan Castillo
authored
on 28 Jan 2015
Dan Handley
committed
on 28 Jan 2015
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Merge pull request #248 from jcastillo-arm/jc/tf-issues/212_1
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Allow BL3-2 to be loaded into the secure region of DRAM
danh-arm
committed
on 28 Jan 2015
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2015-01-22 |
Remove coherent memory from the BL memory maps
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This patch extends the build option `USE_COHERENT_MEMORY` to
conditionally remove coherent memory from the memory maps of
all boot loader stages. The patch also adds necessary
documentation for coherent memory removal in firmware-design,
porting and user guides.
Fixes ARM-Software/tf-issues#106
Change-Id: I260e8768c6a5c2efc402f5804a80657d8ce38773
Soby Mathew
authored
on 8 Jan 2015
Dan Handley
committed
on 22 Jan 2015
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2015-01-21 |
FVP: map non-secure DRAM1 in the MMU
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This patch maps the non-secure region of DRAM1 in the MMU. The
non-secure region comprises the whole DRAM1 (0x80000000 -
0xffffffff) excluding the top 16 MB (0xff000000 - 0xffffffff).
The TrustZone controller configures this 16 MB region as secure
memory, so it can not be accessed in non-secure mode.
The number of MMU tables in BL2 has been increased to 3 because
the new size of the non-secure region in DRAM requires an extra L2
table.
Change-Id: I5ad080c6e181f6b6060e15cebb1d18b7fa128cf5
Juan Castillo
committed
on 21 Jan 2015
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2014-10-22 |
FVP: keep shared data in Trusted SRAM
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This patch deprecates the build option to relocate the shared data
into Trusted DRAM in FVP. After this change, shared data is always
located at the base of Trusted SRAM. This reduces the complexity
of the memory map and the number of combinations in the build
options.
Fixes ARM-software/tf-issues#257
Change-Id: I68426472567b9d8c6d22d8884cb816f6b61bcbd3
Juan Castillo
committed
on 22 Oct 2014
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2014-08-14 |
FVP: make usage of Trusted DRAM optional at build time
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This patch groups the current contents of the Trusted DRAM region at
address 0x00_0600_0000 (entrypoint mailboxes and BL3-1 parameters) in
a single shared memory area that may be allocated to Trusted SRAM
(default) or Trusted DRAM at build time by setting the
FVP_SHARED_DATA_LOCATION make variable. The size of this shared
memory is 4096 bytes.
The combination 'Shared data in Trusted SRAM + TSP in Trusted DRAM'
is not currently supported due to restrictions in the maximum number
of mmu tables that can be created.
Documentation has been updated to reflect these changes.
Fixes ARM-software/tf-issues#100
Change-Id: I26ff04d33ce4cacf8d770d1a1e24132b4fc53ff0
Juan Castillo
committed
on 14 Aug 2014
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2014-08-12 |
FVP: apply new naming conventions to memory regions
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Secure ROM at address 0x0000_0000 is defined as FVP_TRUSTED_ROM
Secure RAM at address 0x0400_0000 is defined as FVP_TRUSTED_SRAM
Secure RAM at address 0x0600_0000 is defined as FVP_TRUSTED_DRAM
BLn_BASE and BLn_LIMIT definitions have been updated and are based on
these new memory regions.
The available memory for each bootloader in the linker script is
defined by BLn_BASE and BLn_LIMIT, instead of the complete memory
region.
TZROM_BASE/SIZE and TZRAM_BASE/SIZE are no longer required as part of
the platform porting.
FVP common definitions are defined in fvp_def.h while platform_def.h
contains exclusively (with a few exceptions) the definitions that are
mandatory in the porting guide. Therefore, platform_def.h now includes
fvp_def.h instead of the other way around.
Porting guide has been updated to reflect these changes.
Change-Id: I39a6088eb611fc4a347db0db4b8f1f0417dbab05
Juan Castillo
committed
on 12 Aug 2014
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2014-07-28 |
Parametrize baudrate and UART clock during console_init()
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This patch adds baud rate and UART clock frequency as parameters
to the pl011 driver api console_init(). This allows each platform
to specify UART clock and baud rate according to their specific
hardware implementation.
Fixes ARM-software/tf-issues#215
Change-Id: Id13eef70a1c530e709b34dd1e6eb84db0797ced2
Soby Mathew
committed
on 28 Jul 2014
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2014-07-10 |
Merge pull request #157 from sandrine-bailleux/sb/tf-issue-109
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TF issue 109
danh-arm
committed
on 10 Jul 2014
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2014-07-01 |
Remove concept of top/bottom image loading
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This concept is no longer required since we now support loading of
images at fixed addresses only.
The image loader now automatically detects the position of the image
inside the current memory layout and updates the layout such that
memory fragmentation is minimised.
The 'attr' field of the meminfo data structure, which used to hold
the bottom/top loading information, has been removed. Also the 'next'
field has been removed as it wasn't used anywhere.
The 'init_bl2_mem_layout()' function has been moved out of common
code and put in BL1-specific code. It has also been renamed into
'bl1_init_bl2_mem_layout'.
Fixes ARM-software/tf-issues#109
Change-Id: I3f54642ce7b763d5ee3b047ad0ab59eabbcf916d
Sandrine Bailleux
committed
on 1 Jul 2014
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2014-06-27 |
Merge pull request #151 from vikramkanigiri/vk/t133-code-readability
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Simplify entry point information generation code on FVP
Andrew Thoelke
committed
on 27 Jun 2014
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2014-06-24 |
Remove all checkpatch errors from codebase
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Exclude stdlib files because they do not follow kernel code style.
Fixes ARM-software/tf-issues#73
Change-Id: I4cfafa38ab436f5ab22c277cb38f884346a267ab
Juan Castillo
committed
on 24 Jun 2014
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Simplify entry point information generation code on FVP
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This patch reworks FVP specific code responsible for determining
the entry point information for BL3-2 and BL3-3 stages when BL3-1
is configured as the reset handler.
Change-Id: Ia661ff0a6a44c7aabb0b6c1684b2e8d3642d11ec
Vikram Kanigiri
committed
on 24 Jun 2014
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2014-06-05 |
fvp: Remove unused 'bl2_el_change_mem_ptr' variable
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'bl2_el_change_mem_ptr' variable is a left over from the former
BL2/BL3-1 interface.
Change-Id: Ib0979c8e2809e103a41f9c5cc4afec7dd21ac9ab
Sandrine Bailleux
committed
on 5 Jun 2014
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2014-05-29 |
Allow platform parameter X1 to be passed to BL3-1
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bl2_main() was overwriting any platform set X1 parameter for BL3-1
with the value zero.
This patch ensure that any platform set value is correctly passed
to BL3-1. The FVP port adds a check to verify this parameter is
being passed correctly.
Fixes ARM-software/tf-issues#173
Change-Id: Ifbcda73d3d41d2b04a4baf5614e9d2d21f1717c8
Andrew Thoelke
committed
on 29 May 2014
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2014-05-23 |
Rename FVP specific files and functions
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FVP specific files and functions containing the word "plat" have been
renamed to use the word "fvp" to distinguish them from the common
platform functionality and porting functions.
Change-Id: I39f9673dab3ee9c74bd18b3e62b7c21027232f7d
Dan Handley
authored
on 15 May 2014
Achin Gupta
committed
on 23 May 2014
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