LuminaSensum/arm-trusted-firmware

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History for arm-trusted-firmware / plat

2017-06-12	d8e919c Browse files » uniphier: support Socionext UniPhier platform ... Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Masahiro Yamada committed on 12 Jun 2017
2017-06-09	c0a70db Browse files » Merge pull request #971 from Xilinx/tegra ... tegra: Fix build errors davidcunado-arm authored on 9 Jun 2017 GitHub committed on 9 Jun 2017
2017-06-08	c906d2a Browse files » Merge pull request #967 from rockchip-linux/rockchip-cleanup-20170606 ... RK3399: Shrink M0 SRAM code to fit in PMUSRAM davidcunado-arm authored on 8 Jun 2017 GitHub committed on 8 Jun 2017
	d20f189 Browse files » tegra: Fix build errors ... The 'impl' variable is guarded by the symbol DEBUG, but used in an INFO level print statement. INFO is defined based on LOG_LEVEL. Hence, builds would fail when - DEBUG=0 && LOG_LEVEL>=LOG_LEVEL_INFO with a variable used but not defined - DEBUG=1 && LOG_LEVEL<LOG_LEVEL_INFO with a variable defined but not used Fixing this by guarding impl with the same condition that guards INFO. Fixes ARM-software/tf-issues#490 Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Soren Brinkmann committed on 8 Jun 2017
	0437c42 Browse files » Merge pull request #970 from vingu-linaro/enable-pmf-rt-instr-hikey ... Enable pmf rt instr hikey danh-arm authored on 8 Jun 2017 GitHub committed on 8 Jun 2017
2017-06-07	84597b5 Browse files » rockchip: check wakeup cpu when resume ... unlike rk3399 and rk3368, there are some rockchip 64bit SOC do not have CPUPD, and pmu_cpuson_entrypoint() is common function for rockchip platform, so we need to check wakeup cpu when resume. Change-Id: I6313e8a9d7c16b03e033414f0cb281646c2159ff Signed-off-by: Lin Huang <hl@rock-chips.com> Lin Huang authored on 11 May 2017 Caesar Wang committed on 7 Jun 2017
	4e836d3 Browse files » rockchip/rk3399: enable PMU_PERILP_PD_EN bit when suspend ... with PMU_PERILP_PD_EN bit enable, the soc will shutdown cm0, crypto, dcf, imem(normal SRAM), dmac, bootrom, efuse_con, spi, i2c, uart, saradc, tsadc when suspend, we have M0 code need to run when suspend in normal SRAM, so we need to take care of that. Change-Id: I8c066637e5b81d4b1d53197450b9d592cbe00793 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Lin Huang authored on 16 May 2017 Caesar Wang committed on 7 Jun 2017
	af27fb8 Browse files » rockchip/rk3399: Move DRAM restore to PMUSRAM ... This moves the DRAM restore code to PMUSRAM. This is so that the voltage domain that contains the SRAM that it was stored in before may be turned off during system suspend. Change-Id: Id761181a30caadd12f1ce061d1034f3159a76d28 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 16 May 2017 Caesar Wang committed on 7 Jun 2017
	c82eef6 Browse files » rockchip/rk3399: convert to for-loops to save code space ... This converts two functions to use for-loops. This saves a bit of space to help moving DRAM resume code to PMUSRAM. Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 13 May 2017 Caesar Wang committed on 7 Jun 2017
	87aad73 Browse files » rockchip/rk3399: Remove unneeded if statement ... The removed if statement would make the same check that the for loop it is in does to break out of the for loop, so it doesn't make any sense to keep it there. Change-Id: I819c29f9182e6de1fc47e418aed15ad38e8f9fa9 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 11 May 2017 Caesar Wang committed on 7 Jun 2017
	18f705f Browse files » rockchip/rk3399: Remove unneeded register sets ... This removes the mmio_... function calls to set the multicast bit for the PHY registers when overriding the write leveling values. These are not needed since multicast is set by default when calling the function, and it's also better not to leave the side effect of disabling multicast when exiting the function. Change-Id: I83e089a2a2d55268b3832f36724c3b2c4be81082 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 11 May 2017 Caesar Wang committed on 7 Jun 2017
	7d1b3f5 Browse files » rockchip/rk3399: remove unneeded DDR restore function ... This removes the phy_dll_bypass_set function as it is unneeded. The values that function sets are saved during suspend, so the proper values will be restored on resume. Change-Id: I17542206c56e639ce8cb6375233145167441d4e2 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 7 May 2017 Caesar Wang committed on 7 Jun 2017
	60400fc Browse files » rockchip/rk3399: Save space for DRAM suspend data ... This removes the space allocation for the unused PHY register space. For instance in PHY registers 0-127, only 0-90 are used, so don't save the 91-127 registers. This saves about 1.6KB of space. Change-Id: I0c9f6d9bed8f0c1f3b8b805dfb10cf0c06208919 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Derek Basehore authored on 5 May 2017 Caesar Wang committed on 7 Jun 2017
	bc5c300 Browse files » rockchip: add pmusram section ... the function pmu_cpuon_entrypoint() need to run in the pmusram, we just copy bin file to pmusram before, now we add pmusram section and link pmu_cpuon_entrypoint() to pmusram directly Change-Id: Iae31e4c01c480c8e6f565a8f588332b478efdb16 Signed-off-by: Lin Huang <hl@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Lin Huang authored on 4 May 2017 Caesar Wang committed on 7 Jun 2017
	a9059b9 Browse files » rockchip/rk3399: fix DRAM gate training issue ... The differential signal of DQS need keep low level before gate training. It need enable RPULL and disable PHY side ODT to ensure it when do gate training. But it can not access the PHY registers to do it when perform DFS.So the workaroud as below: It is ensure that the PHY's read gate is landing somewhere in the incoming DQS's pulses before it starts searching for pre-amble window. It need get the rddqs_delay_ps to calculate the start point of gate training for DFS. Change-Id: I79eabcf4ec9a9c8f4539f68a51f22afba49c72fe Signed-off-by: Lin Huang <hl@rock-chips.com> Lin Huang authored on 22 Feb 2017 Caesar Wang committed on 7 Jun 2017
	28b02e2 Browse files » hikey960: support BL31 ... Support BL31 on HiKey960 platform. Implement PSCI. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Haojian Zhuang committed on 7 Jun 2017
	7cb09cb Browse files » hikey960: support BL2 ... BL2 loads MCU firmware & BL31 on hikey960 platform. The MCU firmware is used to implement low power feature. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Haojian Zhuang committed on 7 Jun 2017
	2f2abcf Browse files » hikey960: support BL1 on hikey960 platform ... Support BL1 on HiKey960 platform. When recovery mode is detected, BL1 loads NS BL1U that flushs images into UFS. When normal boot mode is detected, BL1 loads BL2. Fix for https://github.com/ARM-software/tf-issues/issues/486 Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Haojian Zhuang committed on 7 Jun 2017
	9f505cc Browse files » hikey: enable PMF and instrumentations ... enable PMF service call and instrumetion for hikey platform Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Vincent Guittot committed on 7 Jun 2017
2017-06-05	b32e6b2 Browse files » Merge pull request #963 from soby-mathew/sm/scmi_dev ... Add SCMI power domain and system power protocol support danh-arm authored on 5 Jun 2017 GitHub committed on 5 Jun 2017
	c66f4ad Browse files » Merge pull request #961 from jeenu-arm/gic-600 ... Introduce ARM GIC-600 driver danh-arm authored on 5 Jun 2017 GitHub committed on 5 Jun 2017
	03dd639 Browse files » Merge pull request #960 from jeenu-arm/cpu-libs ... Add support for Cortex-A75 and Cortex-A55 CPUs danh-arm authored on 5 Jun 2017 GitHub committed on 5 Jun 2017
	40111d4 Browse files » Add SCMI support for Juno platform ... This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_map` array. Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Soby Mathew committed on 5 Jun 2017
	c04a3b6 Browse files » CSS: Add SCMI driver for SCP ... This patch adds the SCMI driver for communicating with SCP. The power domain management and system power management protocol of the SCMI specification[1] is implemented in the driver. The SCP power management abstraction layer for SCMI for CSS power management is also added. A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI driver over SCPI. [1] ARM System Control and Management Interface v1.0 (SCMI) Document number: ARM DEN 0056A Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb Signed-off-by: Soby Mathew <soby.mathew@arm.com> Soby Mathew committed on 5 Jun 2017
2017-06-01	e1c59ab Browse files » Introduce ARM GIC-600 driver ... ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Jeenu Viswambharan committed on 1 Jun 2017
	d40ab48 Browse files » Add support for Cortex-A75 and Cortex-A55 CPUs ... Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> David Wang authored on 9 Nov 2016 Jeenu Viswambharan committed on 1 Jun 2017
	0ceb3e1 Browse files » Merge pull request #957 from hzhuang1/finish_hikey_psci ... Finish hikey psci danh-arm authored on 1 Jun 2017 GitHub committed on 1 Jun 2017
2017-05-31	1e54813 Browse files » hikey: pm: finish PSCI hook functions ... This patch is to enable CPU suspend/resume and system level's suspend/resume; also enable system power off state. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Leo Yan authored on 27 May 2017 Haojian Zhuang committed on 31 May 2017
	c78d524 Browse files » hikey: bl31: enable CCI port for cluster 0 ... The cluster 0 doesn't rely on PSCI to enable it; so enable CCI port for cluster 0 in BL31 platform setup flow. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Leo Yan authored on 27 May 2017 Haojian Zhuang committed on 31 May 2017
	a63db3e Browse files » hikey: fix for CPU topology ... Fix for CPU topology so present the CPU core numbers for two clusters; Base on this fixing, the PSCI can maintain correct power states. Signed-off-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Leo Yan authored on 27 May 2017 Haojian Zhuang committed on 31 May 2017