Merge pull request #1653 from JackyBai/master ...

Add NXP i.MX8MQ basic support

plat: imx: Add i.MX8MQ basic support ...

i.MX8MQ is new SOC of NXP's i.MX8M family based on
A53. It can provide industry-leading audio, voice
and video processing for applications that scale
from consumer home audio to industrial building
automation and mobile computers

this patchset add the basic supoort to boot up
the 4 X A53. more feature will be added later.

Signed-off-by: Bai Ping <ping.bai@nxp.com>

Merge pull request #1703 from oscardagrach/hikey960-dmac-fix ...

hikey960: initialize EDMAC and channels

Merge pull request #1705 from chandnich/platform-id ...

plat/arm/sgi: Use platform specific functions to get platform ids

Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12 ...

Update code with latest changes from Marvell LSP 18.12

plat/marvell: update platform LSP version to 18.12.0 ...

Sync the platform code version with current Marvell LSP.

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

a8k: pm: extend MSS_TRIGGER_TIMEOUT ...

Very rarely, during cpuidle operations the following error
is seen: "PM MSG Trigger Timeout".
This is caused by slow handling of message interrutps
in the PM FW running on CM3 (under heavy PM operation load).

This is not a real issue, so we extend the timeout to
avoid the error prints.

Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/59670
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Tested-by: iSoC Platform CI <ykjenk@marvell.com>

plat/marvell: comphy: Add support for SFI on Lane 4 ...

Add static configuration for SFI+ 10Gbps interface on SERDES
Lane 4.
This is just a copy of Lane 2 static values, not optimized.
Board-to-board iperf test shows up to 6Gbps transfer speed.

Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Reviewed-by: Igal Liberman <igall@marvell.com>

fix: a3900: pm: fix number of CPU power switches. ...

- Number of open power switches for CPUs should be three
  and now two.

- This patch updates the value of open power switches from
  0xfd (two power-switches) to 0xfc (three power-switches).

Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

svc: Update the EEPROM AVS values processing ...

Add support for SVC test builds for tuning AVS values.
Update the SVC procedure and add EEPROM access.
Add support for AP807 AVS values (10 bits wide).

Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

ble: ap807: Switch to PLL mode and update CPU frequency ...

- Update CPU frequency on AP807 to 2GHz for SAR 0x0.
- Increase AVS to 0.88V for 2GHz clock

Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

mvebu: cp110: avoid pcie power on/off sequence when called from Linux ...

In Armada 8K DB boards, PCIe initialization can be executed only once
because PCIe reset performed during chip power on and it cannot be
executed via GPIO later.
This means that power on can be executed only once, when it's called
from the bootloader.
Power on:
	Read bit 21 of the mode, it marks if the caller is
	the bootloader or the Linux Kernel.
Power off:
	Check if the comphy was already configured to PCIe, if yes,
	check if the caller is bootloader, if both conditions are true
	(PCIe mode and called by Linux) - skip the power-off.

In addition, fix incorrect documentation describing mode fields -
PCIe width is 3 bits, not 2.

NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work
with it).

Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

plat: marvell: a3700: do not power off cpu due to errata ref #13 ...

Do not power off the CPU1 since there is no way to wake it up
(wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata
Ref #13 [In power saving mode, both cores must be powered off]:
"When Core 0 is on and Core 1 is in power-off state, a Core 1
wake-up resets Core 0 as well and puts Core 0 back to ROM".

To overcome described HW bug instead of powering the CPU off, let it
reach WFI instruction, which is invoked by generic psci_do_cpu_off
function after platform handler finishes. This will put the core in low
power state and give a chance to wake it up.

Before this change, after running secondary kernel via kexec, only one
core was up, now both cores are up.

Change-Id: I87f144867550728055d9b8a2edb84a14539acab7
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

drivers: add tzc380 support ...

Add tzc380 support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>

Merge pull request #1699 from chandnich/sgi-mt-support ...

Add support to implement multi-threaded platforms for SGI

plat/arm/sgi: Use platform specific functions to get platform ids ...

Add two new functions 'plat_arm_sgi_get_platform_id' and
'plat_arm_sgi_get_config_id' which will be implemented by all the
SGI platforms. These functions can be used to determine the part
number and configuration id of the SGI platforms.

In BL2, these functions are used to populate the 'system-id' node.
In BL31, these functions are used to populate the 'sgi_plat_info_t'
structure with the part number and configuration id of the platform.

Change-Id: I3bacda933527724a3b4074ad4ed5b53a81ea4689
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Merge pull request #1701 from chandnich/psci-ops ...

remove weak implemention of 'plat_arm_psci_override_pm_ops'

hikey960: initialize EDMAC and channels ...

This is needed to utilize the DMA controller on the hikey960

Signed-off-by: Ryan Grachek <ryan@edited.us>

Merge pull request #1698 from hzhuang1/rm_emmc_delay ...

Rm emmc delay

plat/arm: remove weak implemention of 'plat_arm_psci_override_pm_ops' function ...

In order to allow Arm platforms to override the default list of PSCI
callbacks, remove the existing weak implementation of
'plat_arm_psci_override_pm_ops' function and let all the Arm platforms
implement their own 'plat_arm_psci_override_pm_ops' function.

For platforms that support SCMI protocol, the function
'css_scmi_override_pm_ops' can be additionally used as well to
override the default PSCI callbacks.

Change-Id: If7c27468bd51a00ea9c2a3716b5894163f5a9f3c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Merge pull request #1696 from satheesbalya-arm/sb1/sb1_2406_romlib_juno ...

romlib: Add juno support for romlib

plat/arm/sgi: allow value of PLAT_MAX_PWR_LVL to be platform specific ...

For platforms with multi-threaded CPUs, the number of power domains
supported would be more than the value currently defined by
PLAT_MAX_PWR_LVL. So move the PLAT_MAX_PWR_LVL macro to platform
specific code and let the platform define the number of power domain
levels.

Change-Id: I21c0682e62b397860b2999031a0c9c5ce0d28eed
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

plat/arm/sgi: override weak implementation of plat_arm_get_cpu_pe_count ...

To support platforms which are based on multi-threaded CPUs, override
the weak implementation of plat_arm_get_cpu_pe_count function to return
the number of threads supported by the CPU used in the platform.

Change-Id: Ia680773f1277b17e2d3d2414d87943dcece33e89
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

plat/css: allow platforms to define the system power domain level ...

The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain
level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the
system power domain level can be different for CSS platforms that
use multi-threaded CPUs.

So, in preparation towards adding support for platforms that use
multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL
such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the
CSS platform.

Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Merge pull request #1697 from antonio-nino-diaz-arm/an/arch ...

Synchronise arch.h and arch_helpers.h with TF-A-Tests

Synchronise arch.h and arch_helpers.h with TF-A-Tests ...

The headers forked at some point in the past and have diverged a lot. In
order to make it easier to share code between TF-A-Tests and TF-A, this
patch synchronises most of the definitions in the mentioned headers.

This is not a complete sync, it has to be followed by more cleanup.

This patch also removes the read helpers for the AArch32 instructions
ats1cpr and ats1hr (they are write-only).

Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

hikey: remove delay after eMMC initialized ...

commit 386b14b
Author: Haojian Zhuang <haojian.zhuang@linaro.org>
Date:   Wed Nov 21 09:19:49 2018 +0800

    mmc: poll eMMC status after EXT_CSD command

    EXT_CSD command needs to access data from eMMC device. Add the
    operation of polling eMMC device status. Make sure the command is
    finished.

    Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

A hacked delay time can't fit each eMMC device. Since the above commit
enables the polling operation, remove the hacked delay time now.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

juno: Add romlib support ...

This patch adds support to build a combined BL1
and ROMLIB binary file with the right page
alignment in Juno. When USE_ROMLIB=1 is set for
Juno, it generates the combined file
bl1_romlib.bin which needs to be used instead of
bl1.bin

Change-Id: I407efbe48d3e522fa6ef855538a9587193cb1919
Signed-off-by: Sathees Balya <sathees.balya@arm.com>

Merge pull request #1681 from Andre-ARM/allwinner/fixes ...

allwinner: clock / power fixes

Merge pull request #1691 from vijayenthiran-arm/sgi-dmc620-tzc ...

Add support for dmc620 tzc driver