2020-03-09 |
cpus: denver: fixup register used to store return address
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The denver_enable_dco and denver_disable_dco use register X3 to store
the return address. But X3 gets over-written by other functions,
downstream.
This patch stores the return address to X18 instead, to fix this
anomaly.
Change-Id: Ic40bfc1d9abaa7b90348843b9ecd09521bb4ee7b
Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
Kalyani Chidambaram
authored
on 8 Oct 2018
Varun Wadekar
committed
on 9 Mar 2020
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2020-03-03 |
SPMD: Adds partially supported EL2 registers.
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This patch adds EL2 registers that are supported up to ARMv8.6.
ARM_ARCH_MINOR has to specified to enable save/restore routine.
Note: Following registers are still not covered in save/restore.
* AMEVCNTVOFF0<n>_EL2
* AMEVCNTVOFF1<n>_EL2
* ICH_AP0R<n>_EL2
* ICH_AP1R<n>_EL2
* ICH_LR<n>_EL2
Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 3 Mar 2020
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2020-03-02 |
SPMD: save/restore EL2 system registers.
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NOTE: Not all EL-2 system registers are saved/restored.
This subset includes registers recognized by ARMv8.0
Change-Id: I9993c7d78d8f5f8e72d1c6c8d6fd871283aa3ce0
Signed-off-by: Jose Marinho <jose.marinho@arm.com>
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Max Shvetsov
committed
on 2 Mar 2020
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2020-02-25 |
Merge changes from topic "console_t_cleanup" into integration
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* changes:
coreboot: Use generic base address
skeletton: Use generic console_t data structure
cdns: Use generic console_t data structure
Mark Dykes
authored
on 25 Feb 2020
TrustedFirmware Code Review
committed
on 25 Feb 2020
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coreboot: Use generic base address
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Since now the generic console_t structure holds the UART base address as
well, let's use that generic location for the coreboot memory console.
This removes the base member from the coreboot specific data structure,
but keeps the struct console_cbmc_t and its size member.
Change-Id: I7f1dffd41392ba3fe5c07090aea761a42313fb5b
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Andre Przywara
committed
on 25 Feb 2020
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2020-02-24 |
Read-only xlat tables for BL31 memory
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This patch introduces a build flag which allows the xlat tables
to be mapped in a read-only region within BL31 memory. It makes it
much harder for someone who has acquired the ability to write to
arbitrary secure memory addresses to gain control of the
translation tables.
The memory attributes of the descriptors describing the tables
themselves are changed to read-only secure data. This change
happens at the end of BL31 runtime setup. Until this point, the
tables have read-write permissions. This gives a window of
opportunity for changes to be made to the tables with the MMU on
(e.g. reclaiming init code). No changes can be made to the tables
with the MMU turned on from this point onwards. This change is also
enabled for sp_min and tspd.
To make all this possible, the base table was moved to .rodata. The
penalty we pay is that now .rodata must be aligned to the size of
the base table (512B alignment). Still, this is better than putting
the base table with the higher level tables in the xlat_table
section, as that would cost us a full 4KB page.
Changing the tables from read-write to read-only cannot be done with
the MMU on, as the break-before-make sequence would invalidate the
descriptor which resolves the level 3 page table where that very
descriptor is located. This would make the translation required for
writing the changes impossible, generating an MMU fault.
The caches are also flushed.
Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com>
Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
Petre-Ionut Tudor
committed
on 24 Feb 2020
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2020-02-21 |
Merge "Add Matterhorn CPU lib" into integration
joanna.farley
authored
on 21 Feb 2020
TrustedFirmware Code Review
committed
on 21 Feb 2020
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Merge "Add CPULib for Klein Core" into integration
joanna.farley
authored
on 21 Feb 2020
TrustedFirmware Code Review
committed
on 21 Feb 2020
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2020-02-20 |
cpus: higher performance non-cacheable load forwarding
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The CPUACTLR_EL1 register on Cortex-A57 CPUs supports a bit to enable
non-cacheable streaming enhancement. Platforms can set this bit only
if their memory system meets the requirement that cache line fill
requests from the Cortex-A57 processor are atomic.
This patch adds support to enable higher performance non-cacheable load
forwarding for such platforms. Platforms must enable this support by
setting the 'A57_ENABLE_NONCACHEABLE_LOAD_FWD' flag from their
makefiles. This flag is disabled by default.
Change-Id: Ib27e55dd68d11a50962c0bbc5b89072208b4bac5
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Varun Wadekar
committed
on 20 Feb 2020
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2020-02-18 |
coverity: fix MISRA violations
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Fixes for the following MISRA violations:
- Missing explicit parentheses on sub-expression
- An identifier or macro name beginning with an
underscore, shall not be declared
- Type mismatch in BL1 SMC handlers and tspd_main.c
Change-Id: I7a92abf260da95acb0846b27c2997b59b059efc4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Zelalem
committed
on 18 Feb 2020
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Add Matterhorn CPU lib
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Also update copyright statements
Change-Id: Iba0305522ac0f2ddc4da99127fd773f340e67300
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Jimmy Brisson
committed
on 18 Feb 2020
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Add CPULib for Klein Core
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Change-Id: I686fd623b8264c85434853a2a26ecd71e9eeac01
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Jimmy Brisson
committed
on 18 Feb 2020
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2020-02-11 |
Merge changes from topic "lm/fconf" into integration
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* changes:
arm-io: Panic in case of io setup failure
MISRA fix: Use boolean essential type
fconf: Add documentation
fconf: Move platform io policies into fconf
fconf: Add mbedtls shared heap as property
fconf: Add TBBR disable_authentication property
fconf: Add dynamic config DTBs info as property
fconf: Populate properties from dtb during bl2 setup
fconf: Load config dtb from bl1
fconf: initial commit
Sandrine Bailleux
authored
on 11 Feb 2020
TrustedFirmware Code Review
committed
on 11 Feb 2020
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2020-02-07 |
fconf: Add mbedtls shared heap as property
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Use the firmware configuration framework in arm dynamic configuration
to retrieve mbedtls heap information between bl1 and bl2.
For this, a new fconf getter is added to expose the device tree base
address and size.
Change-Id: Ifa5ac9366ae100e2cdd1f4c8e85fc591b170f4b6
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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fconf: Add TBBR disable_authentication property
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Use fconf to retrieve the `disable_authentication` property.
Move this access from arm dynamic configuration to bl common.
Change-Id: Ibf184a5c6245d04839222f5457cf5e651f252b86
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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fconf: Add dynamic config DTBs info as property
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This patch introduces a better separation between the trusted-boot
related properties, and the dynamic configuration DTBs loading
information.
The dynamic configuration DTBs properties are moved to a new node:
`dtb-registry`. All the sub-nodes present will be provided to the
dynamic config framework to be loaded. The node currently only contains
the already defined configuration DTBs, but can be extended for future
features if necessary.
The dynamic config framework is modified to use the abstraction provided
by the fconf framework, instead of directly accessing the DTBs.
The trusted-boot properties are kept under the "arm,tb_fw" compatible
string, but in a separate `tb_fw-config` node.
The `tb_fw-config` property of the `dtb-registry` node simply points
to the load address of `fw_config`, as the `tb_fw-config` is currently
part of the same DTB.
Change-Id: Iceb6c4c2cb92b692b6e28dbdc9fb060f1c46de82
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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fconf: Populate properties from dtb during bl2 setup
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Use the dtb provided by bl1 as configuration file for fconf.
Change-Id: I3f466ad9b7047e1a361d94e71ac6d693e31496d9
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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fconf: Load config dtb from bl1
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Move the loading of the dtb from arm_dym_cfg to fconf. The new loading
function is not associated to arm platform anymore, and can be moved
to bl_main if wanted.
Change-Id: I847d07eaba36d31d9d3ed9eba8e58666ea1ba563
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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fconf: initial commit
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Introduce the Firmware CONfiguration Framework (fconf).
The fconf is an abstraction layer for platform specific data, allowing
a "property" to be queried and a value retrieved without the requesting
entity knowing what backing store is being used to hold the data.
The default backing store used is C structure. If another backing store
has to be used, the platform integrator needs to provide a "populate()"
function to fill the corresponding C structure.
The "populate()" function must be registered to the fconf framework with
the "FCONF_REGISTER_POPULATOR()". This ensures that the function would
be called inside the "fconf_populate()" function.
A two level macro is used as getter:
- the first macro takes 3 parameters and converts it to a function
call: FCONF_GET_PROPERTY(a,b,c) -> a__b_getter(c).
- the second level defines a__b_getter(c) to the matching C structure,
variable, array, function, etc..
Ex: Get a Chain of trust property:
1) FCONF_GET_PROPERY(tbbr, cot, BL2_id) -> tbbr__cot_getter(BL2_id)
2) tbbr__cot_getter(BL2_id) -> cot_desc_ptr[BL2_id]
Change-Id: Id394001353ed295bc680c3f543af0cf8da549469
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
Louis Mayencourt
committed
on 7 Feb 2020
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2020-02-05 |
coverity: Fix MISRA null pointer violations
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Fix code that violates the MISRA rule:
MISRA C-2012 Rule 11.9: Literal "0" shall not be used as
null pointer constant.
The fix explicitly checks whether a pointer is NULL.
Change-Id: Ibc318dc0f464982be9a34783f24ccd1d44800551
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Zelalem
committed
on 5 Feb 2020
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2020-02-04 |
Merge "Coverity: remove unnecessary header file includes" into integration
Mark Dykes
authored
on 4 Feb 2020
TrustedFirmware Code Review
committed
on 4 Feb 2020
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Merge changes from topic "mp/separate_nobits" into integration
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* changes:
plat/arm: Add support for SEPARATE_NOBITS_REGION
Changes necessary to support SEPARATE_NOBITS_REGION feature
Sandrine Bailleux
authored
on 4 Feb 2020
TrustedFirmware Code Review
committed
on 4 Feb 2020
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Coverity: remove unnecessary header file includes
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This patch removes unnecessary header file includes
discovered by Coverity HFA option.
Change-Id: I2827c37c1c24866c87db0e206e681900545925d4
Signed-off-by: Zelalem <zelalem.aweke@arm.com>
Zelalem
committed
on 4 Feb 2020
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coverity: debugfs devfip remove comparisons to LONG_MAX
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CID 353228: Integer handling issues (CONSTANT_EXPRESSION_RESULT)
The checks on size and offset_address in get_entry always resolve to
false provided those fields are long long int and cannot be greater
than LONG_MAX.
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I0fac485a39ac4a40ae8c0d25a706ad74c795e130
Olivier Deprez
committed
on 4 Feb 2020
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2020-02-03 |
Merge "FDT wrappers: add functions for read/write bytes" into integration
Manish Pandey
authored
on 3 Feb 2020
TrustedFirmware Code Review
committed
on 3 Feb 2020
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FDT wrappers: add functions for read/write bytes
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This patch adds 'fdtw_read_bytes' and 'fdtw_write_inplace_bytes'
functions for read/write array of bytes from/to a given property.
It also adds 'fdt_setprop_inplace_namelen_partial' to jmptbl.i
files for builds with USE_ROMLIB=1 option.
Change-Id: Ied7b5c8b38a0e21d508aa7bcf5893e656028b14d
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Alexei Fedorov
committed
on 3 Feb 2020
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2020-01-30 |
Merge "Use correct type when reading SCR register" into integration
Alexei Fedorov
authored
on 30 Jan 2020
TrustedFirmware Code Review
committed
on 30 Jan 2020
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2020-01-29 |
Merge "qemu: Implement PSCI_CPU_OFF." into integration
Soby Mathew
authored
on 29 Jan 2020
TrustedFirmware Code Review
committed
on 29 Jan 2020
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Merge "T589: Fix insufficient ordering guarantees in bakery lock" into integration
Soby Mathew
authored
on 29 Jan 2020
TrustedFirmware Code Review
committed
on 29 Jan 2020
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qemu: Implement PSCI_CPU_OFF.
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This is based on the rpi implementation from
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/2746.
Signed-off-by: Andrew Walbran <qwandor@google.com>
Change-Id: I5fe324fcd9d5e232091e01267ea12147c46bc9c1
Andrew Walbran
committed
on 29 Jan 2020
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