Merge "Enable -Wlogical-op always" into integration

Merge "Enable -Wshadow always" into integration

Enable -Wlogical-op always ...

-Wlogical-op prevents common errors with using numerical constants where
a boolean one is expected as well as when the operands of a logical
operator are the same. While these are perfectly valid behavior, they
can be a sign that something is slightly off.

This patch adds this warning to gcc and it's closest equivalent to
clang, while also fixing any warnings that enabling them causes.

Change-Id: Iabadfc1e6ee0c44eef6685a23b0aed8abef8ce89
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

Enable -Wshadow always ...

Variable shadowing is, according to the C standard, permitted and valid
behaviour. However, allowing a local variable to take the same name as a
global one can cause confusion and can make refactoring and bug hunting
more difficult.

This patch moves -Wshadow from WARNING2 into the general warning group
so it is always used. It also fixes all warnings that this introduces
by simply renaming the local variable to a new name

Change-Id: I6b71bdce6580c6e58b5e0b41e4704ab0aa38576e
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>

GIC-600: Fix include ordering according to the coding style ...

Change-Id: Ia120bcaacea3a462ab78db13f84ed23493033601
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

GIC-600: Fix power up sequence ...

Arm's GIC-600 features a Power Register (GICR_PWRR),
which needs to be programmed to enable redistributor
operation. Section 3.6.1 in the GIC-600 TRM describes
the power-up and power-down sequence in pseudo code,
which deviates from the current TF-A implementation
in drivers/arm/gic/v3/gic600.c.
For powering on a redistributor, the pseudo code suggests
to loop over the whole sequence (check for transition,
write request bit) instead of just looping over the
ready bit read as TF-A does in gic600_pwr_on().
This patch fixes GIC-600 power up sequence according
to the TRM.

Change-Id: I445c480e96ba356b69a2d8e5308ffe6c0a97f45b
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "TF-A: Fix non-standard frequency issue in udelay" into integration

TF-A: Fix non-standard frequency issue in udelay ...

Previous implementation of timers assumed that clk_div has pretty
representation in MHz (10MHz, 100MHz, etc). Unusual frequencies
(99.99MHz) were causing assertion error and made udelay unusable.

Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
Change-Id: Ic915fff224369d113fd9f8edbcfff169fca8beac

Merge changes from topic "gic600_multichip" into integration ...

* changes:
  gic/gic600: add support for multichip configuration
  plat/arm/gicv3: add support for probing multiple GIC Redistributor frames

gic/gic600: add support for multichip configuration ...

Add support to configure GIC-600's multichip routing table registers.
Introduce a new gic600 multichip structure in order to support platforms
to pass their GIC-600 multichip information such as routing table owner,
SPI blocks ownership.

This driver is currently experimental and the driver api may change in
the future.

Change-Id: Id409d0bc07843e271ead3fc2f6e3cb38b317878d
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

SMMUv3:Changed retry loop to delay timer(GENFW-3329) ...

Instead of retry polling, timer of 1ms is used to poll

Signed-off-by: Deepika Bhavnani <deepika.bhavnani@arm.com>
Change-Id: I7e028dc68138d2888e3cf0cbed744f5e6bc6ff42

Correct UART PL011 initialization calculation ...

Currently for Armv7 plaforms the quotient calculated in pl011
uart init code is moved to register r1.

This patch moves the quotient to register r2 as done for other
platforms in the udiv instruction. Value of register r2 is then
used to calculate the values for IBRD and FBRD register

Change-Id: Ie6622f9f0e6d634378b471df5d02823b492c8a24
Signed-off-by: Avinash Mehta <avinash.mehta@arm.com>

gpio: stm32_gpio: do not mix error code types ...

Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>

mmc: increase delay between ACMD41 retries ...

In the SD Specification, Power Up Diagram of Card figure, the Timeout
value for initialization process (ACMD41 command retries) is 1 second.
Align to match MMC cards (in mmc_send_op_cond()) and Linux kernel code,
and set the delay between ACMD41 command retries to 10ms.

Change-Id: I2e07cb9944e7d7b72f2d4b13e0505e6751458091
Signed-off-by: Yann Gautier <yann.gautier@st.com>

Merge changes from topic "ld/stm32-authentication" into integration ...

* changes:
  stm32mp1: add authentication support for stm32image
  bsec: move bsec_mode_is_closed_device() service to platform
  crypto: stm32_hash: Add HASH driver

Merge changes from topic "amlogic-g12a" into integration ...

* changes:
  amlogic: g12a: Add support for the S905X2 (G12A) platform
  amlogic: makefile: Use PLAT variable when possible
  amlogic: sha_dma: Move register mappings to platform header

Merge "GICv3 driver: Fix support for full SPI range" into integration

Merge changes from topic "mp/giv3-discovery" into integration ...

* changes:
  Migrate ARM platforms to use the new GICv3 API
  Adding new optional PSCI hook pwr_domain_on_finish_late
  GICv3: Enable multi socket GIC redistributor frame discovery

Merge changes I0283fc2e,Ib476d024,Iada05f7c into integration ...

* changes:
  hikey: fix to load FIP by partition table.
  hikey960: fix to load FIP by partition table
  drivers: partition: support different block size

GICv3: Enable multi socket GIC redistributor frame discovery ...

This patch provides declaration and definition of new GICv3 driver
API: gicv3_rdistif_probe().This function delegates the responsibility
of discovering the corresponding Redistributor base frame to each CPU
itself. It is a modified version of gicv3_rdistif_base_addrs_probe()
and is executed by each CPU in the platform unlike the previous
approach in which only the Primary CPU did the discovery of all the
Redistributor frames for every CPU.

The flush operations as part of gicv3_driver_init() function are
made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY
because the GICv3 driver data structure contents are accessed by CPU
with D-Cache turned off during power down operations.

Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

stm32mp1: add authentication support for stm32image ...

This commit adds authentication binary support for STM32MP1.
It prints the bootrom authentication result if signed
image is used and authenticates the next loaded STM32 images.
It also enables the dynamic translation table support
(PLAT_XLAT_TABLES_DYNAMIC) to use bootrom services.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: Iba706519e0dc6b6fae1f3dd498383351f0f75f51

bsec: move bsec_mode_is_closed_device() service to platform ...

This BSEC service is a platform specific service. Implementation
moved to the platform part.

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I1f70ed48a446860498ed111acce01187568538c9

crypto: stm32_hash: Add HASH driver ...

The driver manages the HASH processor IP on STM32MP1

Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585

drivers: partition: support different block size ...

The block size of some storage device is 4096-byte long, such as UFS. But
PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by
PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3

amlogic: sha_dma: Move register mappings to platform header ...

The registers location for the SHA DMA driver is not unique for the
different platforms. Move the mapping out of the driver and into the
platform-specific header.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Change-Id: Ice64637844a3cb384b01e466cb8c1cea5f764129

rpi3: Move rng driver to drivers ...

To allow sharing the driver between the RPi3 and RPi4, move the random
number generator driver into the generic driver directory.

Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

rpi3: Move VC mailbox driver into generic drivers directory ...

To allow sharing the driver between the RPi3 and RPi4, move the mailbox
driver into the generic driver directory.

Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

GICv3 driver: Fix support for full SPI range ...

This patch fixes GICv3 driver bug which causes assertion
when full range of SPI INTIDs 32-1019 is supported in
GICv3 implementation.

Change-Id: Ib6da4b6eea868cff271cb32c7c7570bf5547ab47
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

Merge "stm32mp1: manage CONSOLE_FLAG_TRANSLATE_CRLF and cleanup driver" into integration

Remove RSA PKCS#1 v1.5 support from cert_tool ...

Support for PKCS#1 v1.5 was deprecated in SHA 1001202 and fully removed
in SHA fe199e3, however, cert_tool is still able to generate
certificates in that form. This patch fully removes the ability for
cert_tool to generate these certificates.

Additionally, this patch also fixes a bug where the issuing certificate
was a RSA and the issued certificate was EcDSA. In this case, the issued
certificate would be signed using PKCS#1 v1.5 instead of RSAPSS per
PKCS#1 v2.1, preventing TF-A from verifying the image signatures. Now
that PKCS#1 v1.5 support is removed, all certificates that are signed
with RSA now use the more modern padding scheme.

Change-Id: Id87d7d915be594a1876a73080528d968e65c4e9a
Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>