LuminaSensum/arm-trusted-firmware

Fork: 0

LuminaSensum / arm-trusted-firmware

History for arm-trusted-firmware / plat

2019-12-13	eb75518 Browse files » allwinner: Enable clock before resetting I2C/RSB ... The clock must be running for the module to be reset. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ic8fafc946f3a1a697174b91288e357ffa033ab9a Samuel Holland committed on 13 Dec 2019
	1a43396 Browse files » Merge "allwinner: Fix incorrect ARISC code patch offset check" into integration Soby Mathew authored on 13 Dec 2019 TrustedFirmware Code Review committed on 13 Dec 2019
	49c71a3 Browse files » Merge "allwinner: power: Add DLDO4 power rail" into integration Sandrine Bailleux authored on 13 Dec 2019 TrustedFirmware Code Review committed on 13 Dec 2019
	a47f60f Browse files » Merge "intel: s10: Remove unused source code" into integration Sandrine Bailleux authored on 13 Dec 2019 TrustedFirmware Code Review committed on 13 Dec 2019
2019-12-11	0d1b704 Browse files » intel: s10: Remove unused source code ... remove plat_sip_svc.c and plat_psci.c in stratix 10 platform directory as both has been refactored to common directory for sharing with agilex platform Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I395fed66408f536e8fefd637681e742c63621818 Hadi Asyrafi committed on 11 Dec 2019
2019-12-10	fba54d5 Browse files » Tegra194: smmu: add support for backup multiple smmu regs ... Tegra194 supports multiple SMMU blocks. This patch adds support to save register values for SMMU0 and SMMU2, before entering the System Suspend state. Change-Id: I3a376cdb606ea057ad7047714717245f9dced5cf Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 26 Oct 2017 Varun Wadekar committed on 10 Dec 2019
	8ecc429 Browse files » Tegra194: introduce tegra_mc_def.h ... This patch introduces memory controller register defines for Tegra194 platforms. Change-Id: I6596341ae817b6cec30cb74d201ad854a0c8c0a6 Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com> Pritesh Raithatha authored on 15 Dec 2017 Varun Wadekar committed on 10 Dec 2019
	56c2743 Browse files » Tegra194: 40-bit wide memory address space ... This patch updates the memory address space, physical and virtual, to be 40-bits wide for all Tegra194 platforms. Change-Id: Ie1bcdec2c4e8e15975048ce1c2a31c2ae0dd494c Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 9 Feb 2018 Varun Wadekar committed on 10 Dec 2019
	4719bba Browse files » Tegra194: psci: rename 'percpu_data' variable ... The per CPU wake times are saved in an array called 't19x_percpu_data'. But, there is one instance in the code where the name of the variable is misspelt. This patch fixes this typographical error to fix compilation errors. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I52f5f0b150c51d8cc38372675415dec7944a7735 Varun Wadekar committed on 10 Dec 2019
	953dc54 Browse files » Merge "Use the proper size for tb_fw_cfg_dtb" into integration Alexei Fedorov authored on 10 Dec 2019 TrustedFirmware Code Review committed on 10 Dec 2019
	9be5ca7 Browse files » Merge "arm: Fix current RECLAIM_INIT_CODE behavior" into integration Sandrine Bailleux authored on 10 Dec 2019 TrustedFirmware Code Review committed on 10 Dec 2019
2019-12-09	a71c59d Browse files » arm: Fix current RECLAIM_INIT_CODE behavior ... Previously the .init section was created even when the reclaim flag was manually set to 0. Change-Id: Ia9e7c7997261f54a4eca725d7ea605192f60bcf8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Zelalem Aweke <zelalem.aweke@arm.com> Ambroise Vincent authored on 16 Jul 2019 Zelalem committed on 9 Dec 2019
2019-12-09	6c77dfc Browse files » Use the proper size for tb_fw_cfg_dtb ... Currently tb_fw_cfg_dtb size is fixed to max, which is generally a page (but depend on the platform). Instead, read the actual size of the dtb with the libfdt "fdt_totalsize" function. This avoid flushing extra memory after updating the dtb with mbedtls heap information when shared heap is used. Change-Id: Ibec727661116429f486464a0c9f15e9760d7afe2 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com> Louis Mayencourt committed on 9 Dec 2019
2019-12-06	f224bd4 Browse files » Merge changes from topic "allwinner_bl31_size" into integration ... * changes: Reduce space lost to object alignment imx: Fix multiple definition of ipc_handle imx: Fix missing inclusion of cdefs.h Soby Mathew authored on 6 Dec 2019 TrustedFirmware Code Review committed on 6 Dec 2019
2019-12-04	b3257a3 Browse files » Merge "intel: Refactor common platform code [5/5]" into integration Mark Dykes authored on 4 Dec 2019 TrustedFirmware Code Review committed on 4 Dec 2019
	b33772e Browse files » Merge changes from topic "platform-refactor" into integration ... * changes: intel: Refactor common platform code [4/5] intel: Refactor common platform code [3/5] intel: Refactor common platform code [2/5] intel: Refactor common platform code [1/5] Mark Dykes authored on 4 Dec 2019 TrustedFirmware Code Review committed on 4 Dec 2019
	449aeb6 Browse files » Merge "rockchip: px30: Add support for UART3 as serial output" into integration Manish Pandey authored on 4 Dec 2019 TrustedFirmware Code Review committed on 4 Dec 2019
	118a67a Browse files » imx: Fix multiple definition of ipc_handle ... This is not conforming C and does not compile with -fno-common. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073 Samuel Holland committed on 4 Dec 2019
	e8bb1c2 Browse files » imx: Fix missing inclusion of cdefs.h ... This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a Samuel Holland committed on 4 Dec 2019
	5cffedc Browse files » allwinner: Fix incorrect ARISC code patch offset check ... The current range check for the offset is wrong: it is counting bytes, while indexing an array of uint32_t. Since the offset is always zero, the parameter is unnecessary. Instead of adding more code to fix the check, remove the parameter to avoid the problem entirely. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Iadfc7d027155adc754e017b3462233ce9a1d64f6 Samuel Holland committed on 4 Dec 2019
2019-12-03	87b582e Browse files » Merge "Enable -Wlogical-op always" into integration Manish Pandey authored on 3 Dec 2019 TrustedFirmware Code Review committed on 3 Dec 2019
	f67a297 Browse files » Merge "Enable -Wshadow always" into integration Manish Pandey authored on 3 Dec 2019 TrustedFirmware Code Review committed on 3 Dec 2019
	45d4611 Browse files » Merge "plat/rockchip: initialize reset and poweroff GPIOs with known invalid value" into integration Manish Pandey authored on 3 Dec 2019 TrustedFirmware Code Review committed on 3 Dec 2019
	530a5cb Browse files » Merge changes from topic "tegra-downstream-092319" into integration ... * changes: Tegra194: add support to reset GPU Tegra194: memctrl: fix logic to check TZDRAM config register access Tegra: introduce plat_enable_console() Tegra: include: drivers: introduce spe.h Tegra194: update nvg header to v6.4 Tegra194: mce: enable strict checking Tegra194: CC6 state from last offline CPU in the cluster Tegra194: console driver compilation from platform makefiles Tegra194: memctrl: platform handler for TZDRAM setup Tegra194: memctrl: override SE client as coherent Tegra194: save system suspend entry marker to TZDRAM Tegra194: helper functions for CPU rst handler and SMMU ctx offset Tegra194: cleanup references to Tegra186 Tegra194: mce: display NVG header version during boot Tegra194: mce: fix cg_cstate encoding format Tegra194: drivers: SE and RNG1/PKA1 context save support Tegra194: rename secure scratch register macros Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation Tegra194: mce: remove unsupported functionality Tegra194: sanity check target cluster during core power on Tegra194: fix defects flagged by MISRA scan Tegra194: mce: fix defects flagged by MISRA scan Tegra194: remove the GPU reset register macro Tegra194: MC registers to allow CPU accesses to TZRAM Tegra194: increase MAX_MMAP_REGIONS macro value Tegra194: update nvg header to v6.1 Tegra194: update cache operations supported by the ROC Tegra194: memctrl: platform handlers to reprogram MSS Tegra194: core and cluster count values Tegra194: correct the TEGRA_CAR_RESET_BASE macro value Tegra194: add MC_SECURITY mask defines Tegra194: Update wake mask, wake time for cpu offlining Tegra194: program stream ids for XUSB Tegra194: Update checks for c-state stats Tegra194: smmu: fix mask for board revision id Tegra194: smmu: ISO support Tegra194: Initialize smmu on system suspend exit Tegra194: Update cpu core-id calculation Tegra194: read-modify-write ACTLR_ELx registers Tegra194: Enable fake system suspend Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits Tegra194: platform support for memctrl/smmu drivers Tegra194: Support for cpu suspend Sandrine Bailleux authored on 3 Dec 2019 TrustedFirmware Code Review committed on 3 Dec 2019
2019-11-28	2d1f101 Browse files » Tegra194: add support to reset GPU ... This patch adds macros, to define registers required to support GPU reset, for Tegra194 SoCs. Change-Id: Ifa7e0161b9e8de695a33856193f500b847a03526 Signed-off-by: Jeetesh Burman <jburman@nvidia.com> Jeetesh Burman authored on 22 Jan 2018 Varun Wadekar committed on 28 Nov 2019
	95397d9 Browse files » Tegra194: memctrl: fix logic to check TZDRAM config register access ... This patch fixes the logic to check if the previous bootloader has disabled access to the TZDRAM configuration registers. The polarity for the bit was incorrect in the previous check. Change-Id: I7a0ba4f7b1714997508ece904c0261ca2c901a03 Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 29 Nov 2017 Varun Wadekar committed on 28 Nov 2019
	117dbe6 Browse files » Tegra: introduce plat_enable_console() ... This patch introduces the 'plat_enable_console' handler to allow the platform to enable the right console. Tegra194 platform supports multiple console, while all the previous platforms support only one console. For Tegra194 platforms, the previous bootloader checks the platform config and sets the uart-id boot parameter, to 0xFE. On seeing this boot parameter, the platform port uses the proper memory aperture base address to communicate with the SPE. This functionality is currently protected by a platform macro, ENABLE_CONSOLE_SPE. Change-Id: I3972aa376d66bd10d868495f561dc08fe32fcb10 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Varun Wadekar committed on 28 Nov 2019
	f0222c2 Browse files » Tegra: include: drivers: introduce spe.h ... This patch introduces a header file for the spe-console driver. This file currently provides a device struct and a registration function call for clients. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: Ic65c056f5bd60871d8a3f44f2c1210035f878799 Varun Wadekar committed on 28 Nov 2019
	02b3e31 Browse files » Tegra194: update nvg header to v6.4 ... This patch updates the header, t194_nvg.h, to v6.4. This gets it in synch with MTS pre-release 2 - cl39748439. Change-Id: I1093c9f5dea7b7f230b3267c90b54b7f3005ecd7 Signed-off-by: Steven Kao <skao@nvidia.com> Steven Kao authored on 7 Nov 2017 Varun Wadekar committed on 28 Nov 2019
	ac252f9 Browse files » Tegra194: mce: enable strict checking ... "Strict checking" is a mode where secure world can access secure-only areas unlike legacy mode where secure world could access non-secure spaces as well. Secure-only areas are defined as the TZ-DRAM carveout and any GSC with the CPU_SECURE bit set. This mode not only helps prevent issues with IO-Coherency but aids with security as well. This patch implements the programming sequence required to enable strict checking mode for Tegra194 SoCs. Change-Id: Ic2e594f79ec7c5bc1339b509e67c4c62efb9d0c0 Signed-off-by: Dilan Lee <dilee@nvidia.com> Dilan Lee authored on 10 Aug 2017 Varun Wadekar committed on 28 Nov 2019