drivers/stm32_hash: register resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the HASH instances. Note that only BL32 needs to register the
shared peripheral because BL2 does not embed the shared resources
driver.

Change-Id: I7f78fa8e47da71d48ef8b1dfe4d6f040fe918d8b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32_gpio: register GPIO resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the GPIO pins.

Change-Id: Ifda473bcbbb0af799be6587961d6641edf887605
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32_iwdg: register IWDG resources as secure or not ...

Register in the shared resources driver the secure or non-secure state
of the IWDG instances.

Change-Id: I3a3bc9525447f6a2a465891ca3a3fd5fe664ca07
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/stm32mp_pmic: register PMIC resources as secure or not ...

Register in the shared resources driver the secure or non-secure
state of the PMIC.

Change-Id: Ic1f172ba62785018f8e9bb321782d725e2d2f434
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: st: clock: register parent of secure clocks ...

Introduce stm32mp1_register_clock_parents_secure() in stm32mp1
clock driver to allow platform shared resources to register as
secure the parent clocks of a clock registered as secure.

Change-Id: I53a9ab6aa78ee840ededce67e7b12a84e08ee843
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers/scmi-msg: smt entry points for incoming messages ...

This change implements SCMI channels for reading a SCMI message from a
shared memory and call the SCMI message drivers to route the message
to the target platform services.

SMT refers to the shared memory management protocol which is used
to get/put message/response in shared memory. SMT is a 28byte header
stating shared memory state and exchanged protocol data.

The processing entry for a SCMI message can be a secure interrupt
or fastcall SMCCC invocation.

SMT description in this implementation is based on the OP-TEE
project [1] itself based in the SCP-firmware implementation [2].

Link: [1] https://github.com/OP-TEE/optee_os/commit/a58c4d706d2333d2b21a3eba7e2ec0cb257bca1d
Link: [2] https://github.com/ARM-software/SCP-firmware.git

Change-Id: I416c7dab5c67954c6fe80bae8d8cdfdcda66873e
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

drivers/scmi-msg: support for reset domain protocol ...

Adds SCMI reset domain protocol support in the SCMI message drivers
as defined in SCMI specification v2.0 [1]. Not all the messages
defined in the specification are supported.

scmi_msg_get_rd_handler() sanitizes the message_id value
against any speculative use of reset domain ID as a index since by
SCMI specification, IDs are indices.

This implementation is based on the OP-TEE project implementation [2]
itself based on the SCP-firmware implementation [3] of the SCMI
protocol server side.

Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
Link: [2] https://github.com/OP-TEE/optee_os/commit/56a1f10ed99d683ee3a8af29b6147a59a99ef3e0
Link: [3] https://github.com/ARM-software/SCP-firmware.git

Change-Id: If7cf13de40a815dedb40dcd5af8b6bb6725d9078
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

drivers/scmi-msg: support for clock protocol ...

Adds SCMI clock protocol support in the SCMI message drivers as
defined in SCMI specification v2.0 [1] for clock protocol messages.

Platform can provide one of the plat_scmi_clock_*() handler for the
supported operations set/get state/rate and others.

scmi_msg_get_clock_handler() sanitizes the message_id value
against any speculative use of clock ID as a index since by
SCMI specification, IDs are indices.

This implementation is based on the OP-TEE project implementation [2]
itself based on the SCP-firmware implementation [3] of the SCMI
protocol server side.

Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
Link: [2] https://github.com/OP-TEE/optee_os/commit/a7a9e3ba71dd908aafdc4c5ed9b29b15faa9692d
Link: [3] https://github.com/ARM-software/SCP-firmware.git

Change-Id: Ib56e096512042d4f7b9563d1e4181554eb8ed02c
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

drivers/scmi-msg: driver for processing scmi messages ...

This change introduces drivers to allow a platform to create a basic
SCMI service and register handlers for client request (SCMI agent) on
system resources. This is the first piece of the drivers: an entry
function, the SCMI base protocol support and helpers for create
the response message.

With this change, scmi_process_message() is the entry function to
process an incoming SCMI message. The function expect the message
is already copied from shared memory into secure memory. The message
structure stores message reference and output buffer reference where
response message shall be stored.

scmi_process_message() calls the SCMI protocol driver according to
the protocol ID in the message. The SCMI protocol driver will call
defined platform handlers according to the message content.

This change introduces only the SCMI base protocol as defined in
SCMI specification v2.0 [1]. Not all the messages defined
in the specification are supported.

The SCMI message implementation is derived from the OP-TEE project [2]
itself based on the SCP-firmware implementation [3] of the SCMI protocol
server side.

Link: [1] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/DEN0056A_System_Control_and_Management_Interface.pdf
Link: [2] https://github.com/OP-TEE/optee_os/commit/ae8c8068098d291e6e55744dbc237ec39fd9840a
Link: [3] https://github.com/ARM-software/SCP-firmware/tree/v2.6.0

Change-Id: I639c4154a39fca60606264baf8d32452641f45e9
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

drivers: introduce ST ETZPC driver ...

ETZPC stands for Extended TrustZone Protection Controller. It is a
resource conditional access device. It is mainly based on Arm TZPC.

ST ETZPC exposes memory mapped DECPROT cells to set access permissions
to SoC peripheral interfaces as I2C, SPI, DDR controllers, and some
of the SoC internal memories.

ST ETZPC exposes memory mapped TZMA cells to set access permissions
to some SoC internal memories.

Change-Id: I47ce20ffcfb55306dab923153b71e1bcbe2a5570
Co-developed-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

Merge "drivers: stm32_reset adapt interface to timeout argument" into integration

drivers: stm32_reset adapt interface to timeout argument ...

Changes stm32mp1 reset driver to API to add a timeout argument
to stm32mp_reset_assert() and stm32mp_reset_deassert() and
a return value.

With a supplied timeout, the functions wait the target reset state
is reached before returning. With a timeout of zero, the functions
simply load target reset state in SoC interface and return without
waiting.

Helper functions stm32mp_reset_set() and stm32mp_reset_release()
use a zero timeout and return without a return code.

This change updates few stm32 drivers and plat/stm32mp1 blé_plat_setup.c
accordingly without any functional change.
functional change.

Change-Id: Ia1a73a15125d3055fd8739c125b70bcb9562c27f
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: fix debug trace on clock enable/disable ...

Adds missing terminal new line character '\n' to debug traces,
fix format as index is an unsigned value and use present tense rather
than past tense in the printed message.

Change-Id: I88c06ef4d3a11d97ff8e96875a3dd0f58a3c98b6
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: enable system clocks during initialization ...

Enable few system clocks at related BL initialization.

Change-Id: I12b35e8cdc128b993de4a1dc4c6e9d52624dd8d9
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: prevent crash on always on clocks ...

Oscillators and PLLs are not gated on stm32mp_clk_enable/disable()
calls. This change prevents functions to panic when called for such
always-on clocks. Gating these clocks is out of the scope of
this change.

Change-Id: Ie730553dea480b529de942446176db9119587832
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: add RTC as a gateable clock ...

Adds RTC clock to the list of the supported clocks. This allows
stm32mp_clk_*() API functions to enable, disable and set and get
rate for the clock RTC clock.

Change-Id: I8efc3f00b1f22d1912f59d1846994e9e646d6614
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: support shifted clock selector bit masks ...

The current implementation optimizes memory consumed by gateable
clock table by storing bit mask and bit shift with 1 byte each.
The issue is that register selector bit masks above the 7th LSBit
cannot be stored.

This change uses the shift info to shift the mask before it is used,
allowing clock selector register bit fields to be spread on the 32 bits
of the register as long as the mask fits in 8 contiguous bit at most.

This change is needed to add the RTC clock to the gateable clocks table.

Change-Id: I8a0fbcbf20ea383fb3d712f5064d2d307e44465d
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

drivers: stm32mp1 clocks: allow tree lookup for several system clocks ...

Oscillators, PLLs and some system clocks can be related straight to
a parent clock. Prior this change were only oscillators and few
clocks supported by this look up. This changes adds PLLs and other
system clocks. This enables for flexible use of clock tree exploration
when computing a clock frequency value.

Change-Id: I15ec98023a7095e3120a6954de59a4799d92c66b
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>

plat/stm32: Use generic fdt_get_reg_props_by_name() ...

The STM32 platform port parse DT nodes to find base address to
peripherals. It does this by using its own implementation, even though
this functionality is generic and actually widely useful outside of the
STM32 code.

Re-implement fdt_get_reg_props_by_name() on top of the newly introduced
fdt_get_reg_props_by_index() function, and move it to fdt_wrapper.c.
This is removes the assumption that #address-cells and #size-cells are
always one.

Change-Id: I6d584930262c732b6e0356d98aea50b2654f789d
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

plat/stm32: Implement fdt_read_uint32_default() as a wrapper ...

The STM32 platform code uses its own set of FDT helper functions,
although some of them are fairly generic.

Remove the implementation of fdt_read_uint32_default() and implement it
on top of the newly introduced fdt_read_uint32() function, then convert
all users over.

This also fixes two callers, which were slightly abusing the "default"
semantic.

Change-Id: I570533362b4846e58dd797a92347de3e0e5abb75
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

plat/stm32: Use generic fdt_read_uint32_array() implementation ...

The device tree parsing code for the STM32 platform is using its own FDT
helper functions, some of them being rather generic.
In particular the existing fdt_read_uint32_array() implementation is now
almost identical to the new generic code in fdt_wrappers.c, so we can
remove the ST specific version and adjust the existing callers.

Compared to the original ST implementation the new version takes a
pointer to the DTB as the first argument, and also swaps the order of
the number of cells and the pointer.

Change-Id: Id06b0f1ba4db1ad1f733be40e82c34f46638551a
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

stm32mp1: dynamically map DDR later and non-cacheable during its test ...

A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.

The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.

PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.

BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.

Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>

io: io_stm32image: correct possible NULL pointer dereference ...

This issue was found with cppcheck in our downstream code:
[drivers/st/io/io_stm32image.c:234] -> [drivers/st/io/io_stm32image.c:244]:
 (warning) Either the condition 'buffer!=0U' is redundant or there is
 possible null pointer dereference: local_buffer.

Change-Id: Ieb615b7e485dc93bbeeed4cd8bf845eb84c14ac9
Signed-off-by: Yann Gautier <yann.gautier@st.com>

nand: stm32_fmc2_nand: correct xor_ecc.val assigned value ...

The variable is wrongly set to 0L, whereas it is an unsigned int, it should
then be 0U.

Change-Id: I0b164c0ea598ec8a503f1693da2f3789f59da238
Signed-off-by: Yann Gautier <yann.gautier@st.com>

spi: stm32_qspi: correct static analysis issues ...

Sparse issue:
drivers/st/spi/stm32_qspi.c:445:5:
 warning: symbol 'stm32_qspi_init' was not declared. Should it be static?

Cppcheck issue:
[drivers/st/spi/stm32_qspi.c:175] -> [drivers/st/spi/stm32_qspi.c:187]:
 (style) Variable 'len' is reassigned a value before the old one has been
 used.
[drivers/st/spi/stm32_qspi.c:178]:
 (style) The scope of the variable 'timeout' can be reduced.

Change-Id: I575fb50766355a6717cbd193fc4a80ff1923014c
Signed-off-by: Yann Gautier <yann.gautier@st.com>

stm32: Use generic console_t data structure ...

Since now the generic console_t structure holds the UART base address as
well, let's use that generic location and drop the UART driver specific
data structure at all.

Change-Id: Iea6ca26ff4903c33f0fad27fec96fdbabd4e0a91
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

spi: stm32_qspi: Add QSPI support ...

Add QSPI support (limited to read interface).
Implements the memory map and indirect modes.
Low level driver based on SPI-MEM operations.

Change-Id: Ied698e6de3c17d977f8b497c81f2e4a0a27c0961
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

fmc: stm32_fmc2_nand: Add FMC2 driver support ...

Add fmc2_nand driver support. The driver implements
only read interface for NAND devices.

Change-Id: I3cd037e8ff645ce0d217092b96f33ef41cb7a522
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Christophe Kerello <christophe.kerello@st.com>

io: change seek offset to signed long long ...

IO seek offset can be set to values above UINT32_MAX, this change
changes the seek offset argument from 'ssize_t' to 'signed long long'.
Fixing platform seek functions to match the new interface update.

Change-Id: I25de83b3b7abe5f52a7b0fee36f71e60cac9cfcb
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>

gpio: stm32_gpio: do not mix error code types ...

Change-Id: I84f8a99be2dcdf7c51fbecdb324df8e2f32cc855
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>