Merge pull request #651 from Xilinx/zynqmp_uart ...

zynqmp: Make UART selectable

zynqmp: Add option to select between Cadence UARTs ...

Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd
UART available in the SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

Merge pull request #650 from Xilinx/zynqmp-updates ...

Zynqmp updates

Add support for QEMU virt ARMv8-A target ...

This patch adds support for the QEMU virt ARMv8-A target.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

zynqmp: FSBL->ATF handover ...

Parse the parameter structure the FSBL populates, to populate the bl32
and bl33 image structures.

Cc: Sarat Chand Savitala <saratcha@xilinx.com>
Cc: petalinux-dev@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[ SB
 - pass pointers to structs instead of structs
 - handle execution state parameter
 - populate bl32 SPSR
 - add documentation
 - query bootmode and consider missing handoff parameters an error when
   not in JTAG boot mode
]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Revise memory configuration options ...

Drop the current configuration options for selecting the location of
the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION).
The new configuration provides one default setup (ATF in OCM,
BL32 in DRAM). Additionally, the new configuration options
 - ZYNQMP_ATF_MEM_BASE
 - ZYNQMP_ATF_MEM_SIZE
 - ZYNQMP_BL32_MEM_BASE
 - ZYNQMP_BL32_MEM_SIZE
can be used to freely configure the memory locations used for ATF and
secure payload.

Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE.

Cc: petalinux-dev@xilinx.com
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Alistair Francis <alistair.francis@xilinx.com>

Add support for Xilinx Zynq UltraScale+ MPSOC ...

The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This
patch adds the platform port for that SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

docs: fix the command to compile BL31 on Tegra ...

This patch fixes the command line used to compile BL31 on
Tegra platforms.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra132: set TZDRAM_BASE to 0xF5C00000 ...

The TZDRAM base on the reference platform has been bumped up due to
some BL2 memory cleanup. Platforms can also use a different TZDRAM
base by setting TZDRAM_BASE=<value> in the build command line.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

tlkd: delete 'NEED_BL32' build variable ...

Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a
completely different build system and is present on the device as a
binary blob. The NEED_BL32 flag does not influence the TLK load/boot
sequence at all. Moreover, it expects that TLK binary be present on
the host before we can compile BL31 support for Tegra.

This patch removes the flag from the makefile and thus decouples both
the build systems.

Tested by booting TLK without the NEED_BL32 flag.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Tegra: Support for Tegra's T132 platforms ...

This patch implements support for T132 (Denver CPU) based Tegra
platforms.

The following features have been added:

* SiP calls to switch T132 CPU's AARCH mode
* Complete PSCI support, including 'System Suspend'
* Platform specific MMIO settings
* Locking of CPU vector registers

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Implement get_sys_suspend_power_state() handler for Tegra ...

This patch implements the get_sys_suspend_power_state() handler required by
the PSCI SYSTEM_SUSPEND API. The intent of this handler is to return the
appropriate State-ID field which can be utilized in `affinst_suspend()` to
suspend to system affinity level.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Boot Trusted OS' on Tegra SoCs ...

This patch adds support to run a Trusted OS during boot time. The
previous stage bootloader passes the entry point information in
the 'bl32_ep_info' structure, which is passed over to the SPD.

The build system expects the dispatcher to be passed as an input
parameter using the 'SPD=<dispatcher>' option. The Tegra docs have
also been updated with this information.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Support for NVIDIA's Tegra T210 SoCs ...

T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an
ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active
at a given point in time.

This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch
also adds support to boot secondary CPUs, enter/exit core power states for
all CPUs in the slow/fast clusters. The support to switch between clusters
is still not available in this patch and would be available later.

Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>