Merge pull request #1844 from chandnich/rename_sgiclark ...

css/sgi: replace all uses of Clark with new product names

Merge pull request #1837 from spencercw/master ...

imx: Configure CAAM job rings master ID for i.MX8MQ

Tegra: dummy support for the io_storage backend ...

This patch provides dummy macros and platform files to compile
the io_storage driver backend. This patch is necessary to
remove the "--unresolved=el3_panic" linker flag from Tegra's
makefiles and allow us to revert this workaround, previously
suggested by the ARM toolchain team.

The "--unresolved=el3_panic" flag actually was a big hammer that
allowed Tegra platforms to work with armlink previously but it
masks legit errors with the code as well.

Change-Id: I0421d35657823215229f84231896b84167f90548
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Merge pull request #1815 from Anson-Huang/gic ...

gic: make sure ProcessorSleep bit clear successfully

Merge pull request #1751 from vwadekar/tegra-scatter-file-support ...

Tegra scatter file support

Merge pull request #1845 from ambroise-arm/av/errata ...

Apply workarounds for errata of Cortex-A53, A55 and A57

imx: make sure GIC redistributor is awake before initialization ...

GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.

On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.

This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>

Remove Mbed TLS dependency from plat_bl_common.c ...

Due to the shared Mbed TLS heap optimisation introduced in 6d01a463,
common code files were depending on Mbed TLS specific headers. This
dependency is now removed by moving the default, unoptimised heap
implementation inside the Mbed TLS specific files.

Change-Id: I11ea3eb4474f0d9b6cb79a2afd73a51a4a9b8994
Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>

Minor changes to documentation and comments ...

Fix some typos and clarify some sentences.

Change-Id: Id276d1ced9a991b4eddc5c47ad9a825e6b29ef74
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

juno: Enable CPU errata workarounds ...

Change-Id: I7593f5ed89b9ef13b510e2259c909838c64ec56c
Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>

css/sgi: replace all uses of Clark with new product names ...

Replace all uses of 'SGI_CLARK' with 'RD_N1E1_EDGE' and
'SGI_CLARK_HELIOS' with 'RD_E1_EDGE' as per the updated product
names

Change-Id: Ib8136e421b1a46da1e5df58c6b1432d5c78d279b
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

Tegra: Support for scatterfile for the BL31 image ...

This patch provides support for using the scatterfile format as
the linker script with the 'armlink' linker for Tegra platforms.

In order to enable the scatterfile usage the following changes
have been made:

* provide mapping for ld.S symbols in bl_common.h
* include bl_common.h from all the affected files
* update the makefile rules to use the scatterfile and armlink
  to compile BL31
* update pubsub.h to add sections to the scatterfile

NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY.

Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

Merge pull request #1829 from antonio-nino-diaz-arm/an/pauth ...

Add Pointer Authentication (ARMv8.3-PAuth) support to the TF

Merge pull request #1840 from grandpaul/rpi3-sdhost-improve1 ...

RaspberryPi3 sdhost driver improvement.

plat/arm: Implement ARMv8.3-PAuth interfaces ...

This feature is only supported on FVP.

Change-Id: I4e265610211d92a84bd2773c34acfbe02a1a1826
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

Merge pull request #1838 from chandnich/rename ...

Apply official names to SGI-Clark Platforms

Merge pull request #1834 from thloh85-intel/s10_bl31 ...

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform

Merge pull request #1826 from smaeul/allwinner ...

allwinner: A few minor improvements

board/rde1edge: rename sgiclarkh to rde1edge ...

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarkh' with
'rde1edge' as per the updated product names.

Change-Id: I14e9b0332851798531de21d70eb54f1e5557a7bd
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

board/rdn1edge: rename sgiclarka to rdn1edge ...

Replace all usage of 'sgiclark' with 'rdn1e1edge' and 'sgiclarka' with
'rdn1edge' as per the updated product names.

Change-Id: Idbc157c73477ec32f507ba2d4a4e907d8813374c
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>

rpi3: sdhost: SDHost driver improvement ...

This commit improves the SDHost driver for RPi3 as following:
 * Unblock MMC_CMD(17). Using MMC_CMD(17) is more efficient on
   block reading.
 * In some low probability that SEND_OP_COND might results CRC7
   error. We can consider that the command runs correctly. We don't
   need to retry this command so removing the code for retry.
 * Using MMC_BUS_WIDTH_1 as MMC default value to improve the stability.
 * Increase the clock to 50Mhz in data mode to speed up the io.
 * Change the pull resistors configuration to gain more stability.

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>

plat: intel: Add BL31 support to Intel Stratix10 SoCFPGA platform ...

This adds BL31 support to Intel Stratix10 SoCFPGA platform. BL31 in TF-A
supports:
- PSCI calls to enable 4 CPU cores
- PSCI mailbox calls for FPGA reconfiguration

Signed-off-by: Loh Tien Hock <tien.hock.loh@intel.com>

Merge pull request #1836 from Yann-lms/docs_and_m4 ...

Update documentation for STM32MP1 and add Cortex-M4 support

imx: Configure CAAM job rings master ID for i.MX8MQ ...

For i.MX8MQ B0 revision the default configuration of JRaMID is not valid
to allow the kernel to use the CAAM job rings. This patch sets the
master ID of the Cortex A in the JRaMID registers.

Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>

Merge pull request #1835 from jts-arm/rename ...

Apply official names to new Arm Neoverse cores

Merge pull request #1828 from uarif1/master ...

Introduce Versatile Express FVP platform to arm-trusted-firmware.

stm32mp1: add minimal support for co-processor Cortex-M4 ...

STM32MP1 chip embeds a dual Cortex-A7 and a Cortex-M4.
The support for Cortex-M4 clocks is added when configuring the clock tree.
Some minimal security features to allow communications between A7 and M4
are also added.

Change-Id: I60417e244a476f60a2758f4969700b2684056665
Signed-off-by: Yann Gautier <yann.gautier@st.com>

rcar_gen3: plat: Prevent PCIe hang during L1X config access ...

In case the PCIe controller receives a L1_Enter_PM DLLP, it will
disable the internal PLLs. The system software cannot predict it
and can attempt to perform device config space access across the
PCIe link while the controller is in this transitional state. If
such condition happens, the PCIe controller register access will
trigger ARM64 SError exception.

This patch adds checks for which PCIe controller is enabled,
checks whether the PCIe controller is in such a transitional
state and if so, first completes the transition and then restarts
the instruction which caused the SError.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

plat/arm: Support for Cortex A5 in FVP Versatile Express platform ...

Cortex A5 doesnt support VFP, Large Page addressing and generic timer
which are addressed in this patch. The device tree for Cortex a5
is also included.

Change-Id: I0722345721b145dfcc80bebd36a1afbdc44bb678
Signed-off-by: Usama Arif <usama.arif@arm.com>

plat/arm: Introduce FVP Versatile Express platform. ...

This patch adds support for Versatile express FVP (Fast models).
Versatile express is a family of platforms that are based on ARM v7.
Currently this port has only been tested on Cortex A7, although it
should work with other ARM V7 cores that support LPAE, generic timers,
VFP and hardware divide. Future patches will support other
cores like Cortex A5 that dont support features like LPAE
and hardware divide. This platform is tested on and only expected to
work on single core models.

Change-Id: I10893af65b8bb64da7b3bd851cab8231718e61dd
Signed-off-by: Usama Arif <usama.arif@arm.com>