Merge "doc: Update list of supported FVP platforms" into integration

morello: Add Morello platform documentation ...

Morello platform has a SCP which brings the primary Rainier CPU
out of reset which starts executing at BL31.

This patch provides documentation support for Morello platform.

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I38f596668e2b14862d543fabc04549ff34bfb8a2

doc: Update list of supported FVP platforms ...

Updated the list of supported FVP platform as per latest
FVP platform release.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I45ef79aff147ed598a3a92ab6f6b277f7f70604a

arm_fpga: Add platform documentation ...

As the Arm Ltd. FPGA port is now working for all existing images, add
some documentation file.

Change-Id: I9e2c532ed15bbc121bb54b3dfc1bdfee8f1443a6
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

plat/arm: Use common build flag for using generic sp804 driver ...

SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_VE_USE_SP804_TIMER.

This patch removes platform specific build flag and adds generic
flag `USE_SP804_TIMER` to be set to 1 by platform if needed.

Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integration

Fix broken links to various sections across docs ...

These broken links were found with the help of this command:
$> sphinx-build -M linkcheck . build

A sample broken link is reported as follows:
(line   80) -local-   firmware-design.rst#secure-el1-payloads-and-dispatchers

Change-Id: I5dcefdd4b8040908658115647e957f6c2c5da7c2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

SPM: build OP-TEE as an S-EL1 Secure Partition ...

Provide manifest and build options to boot OP-TEE as a
guest S-EL1 Secure Partition on top of Hafnium in S-EL2.

Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb

docs/fvp: update SGI and RD FVP list ...

Update SGI-575, RD-E1-Edge and RD-N1-Edge FVP versions to 11.10/36 and
add RD-N1-Edge-Dual to the list of supported Arm Fixed Virtual
Platforms.

Change-Id: I9e7e5662324eeefc80d799ca5341b5bc4dc39cbb
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

FVP Doc: Update list of supported FVP platforms ...

This patch adds the following models
 FVP_Base_Neoverse-E1x1
 FVP_Base_Neoverse-E1x2
 FVP_Base_Neoverse-E1x4
to the list of supported FVP platforms.

Change-Id: Ib526a2a735f17724af3a874b06bf69b4ca85d0dd
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

GICv3: GIC-600: Detect GIC-600 at runtime ...

The only difference between GIC-500 and GIC-600 relevant to TF-A is the
differing power management sequence.
A certain GIC implementation is detectable at runtime, for instance by
checking the IIDR register. Let's add that test before initiating the
GIC-600 specific sequence, so the code can be used on both GIC-600 and
GIC-500 chips alike, without deciding on a GIC chip at compile time.

This means that the GIC-500 "driver" is now redundant. To allow minimal
platform support, add a switch to disable GIC-600 support.

Change-Id: I17ea97d9fb05874772ebaa13e6678b4ba3415557
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

plat/arm: Introduce TC0 platform ...

This patch adds support for Total Compute (TC0) platform. It is an
initial port and additional features are expected to be added later.

TC0 has a SCP which brings the primary Cortex-A out of reset
which starts executing BL1. TF-A optionally authenticates the SCP
ram-fw available in FIP and makes it available for SCP to copy.

Some of the major features included and tested in this platform
port include TBBR, PSCI, MHUv2 and DVFS.

Change-Id: I1675e9d200ca7687c215009eef483d9b3ee764ef
Signed-off-by: Usama Arif <usama.arif@arm.com>

docs: Fixes and updates for the v2.3 release ...

A small set of misc changes to ensure correctness before the v2.3
release.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: I5b4e35b3b46616df0453cecff61f5a414951cd62

Add Cortex-A65/AE to the supported FVP list ...

Cortex-A65x4 and Cortex-A65AEx8 is now included in the list of the
supported Arm Fixed Virtual Platforms.

Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: Ibfcaec11bc75549d60455e96858d79b679e71e5e

FVP: Fix BL31 load address and image size for RESET_TO_BL31=1 ...

When TF-A is built with RESET_TO_BL31=1 option, BL31 is the
first image to be run and should have all the memory allocated
to it except for the memory reserved for Shared RAM at the start
of Trusted SRAM.
This patch fixes FVP BL31 load address and its image size for
RESET_TO_BL31=1 option. BL31 startup address should be set to
0x400_1000 and its maximum image size to the size of Trusted SRAM
minus the first 4KB of shared memory.
Loading BL31 at 0x0402_0000 as it is currently stated in
'\docs\plat\arm\fvp\index.rst' causes EL3 exception when the
image size gets increased (i.e. building with LOG_LEVEL=50)
but doesn't exceed 0x3B000 not causing build error.

Change-Id: Ie450baaf247f1577112f8d143b24e76c39d33e91
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>

plat/arm/sgi: introduce number of chips macro ...

Introduce macro 'CSS_SGI_CHIP_COUNT' to allow Arm CSS platforms with
multi-chip support to define number of chiplets on the platform. By
default, this flag is set to 1 and does not affect the existing single
chip platforms.

For multi-chip platforms, override the default value of
CSS_SGI_CHIP_COUNT with the number of chiplets supported on the
platform. As an example, the command below sets the number of chiplets
to two on the RD-N1-Edge multi-chip platform:

export CROSS_COMPILE=<path-to-cross-compiler>
make PLAT=rdn1edge CSS_SGI_CHIP_COUNT=2 ARCH=aarch64 all

Change-Id: If364dc36bd34b30cc356f74b3e97633933e6c8ee
Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>

Adds option to read ROTPK from registers for FVP ...

Enables usage of ARM_ROTPK_LOCATION=regs for FVP board.
Removes hard-coded developer keys. Instead, setting
ARM_ROTPK_LOCATION=devel_* takes keys from default directory.
In case of ROT_KEY specified - generates a new hash and replaces the
original.

Note: Juno board was tested by original feature author and was not tested
for this patch since we don't have access to the private key. Juno
implementation was moved to board-specific file without changing
functionality. It is not known whether byte-swapping is still needed
for this platform.

Change-Id: I0fdbaca0415cdcd78f3a388551c2e478c01ed986
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>

docs: GCC toolchain upgrade to version 9.2-2019.12 ...

This toolchain provides multiple cross compilers and are publicly
available on developer.arm.com

We build TF-A in CI using:
AArch32 bare-metal target (arm-none-eabi)
AArch64 ELF bare-metal target (aarch64-none-elf)

Change-Id: I910200174d5bad985504d1af4a1ae5819b524003
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

doc: Split the User Guide into multiple files ...

The User Guide document has grown organically over time and
now covers a wide range of topics, making it difficult to
skim read and extract information from. Currently, it covers
these topics and maybe a couple more:

- Requirements (hardware, tools, libs)
- Checking out the repo
- Basic build instructions
- A comprehensive list of build flags
- FIP packaging
- Building specifically for Juno
- Firmware update images
- EL3 payloads
- Preloaded BL33 boot flow
- Running on FVPs
- Running on Juno

I have separated these out into a few groups that become new
documents. Broadly speaking, build instructions for the tools,
for TF-A generally, and for specific scenarios are separated.
Content relating to specific platforms (Juno and the FVPs are
Arm-specific platforms, essentially) has been moved into the
documentation that is specific to those platforms, under
docs/plat/arm.

Change-Id: Ica87c52d8cd4f577332be0b0738998ea3ba3bbec
Signed-off-by: Paul Beesley <paul.beesley@arm.com>