Merge "doc: Recommend using C rather than assembly language" into integration

Merge "doc: Correct CPACR.FPEN usage" into integration

doc: add description of "owner" field in SP layout file. ...

Change-Id: Iedaa83ed546eb2476849a8d53f6e05b847a48b23
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>

doc: Correct CPACR.FPEN usage ...

To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0

Workaround for Neoverse N1 erratum 1868343 ...

Neoverse N1 erratum 1868343 is a Cat B erratum, present in older
revisions of the Neoverse N1 processor core.  The workaround is to
set a bit in the CPUACTLR_EL1 system register, which delays instruction
fetch after branch misprediction. This workaround will have a small
impact on performance.

SDEN can be found here:
https://documentation-service.arm.com/static/5f2c130260a93e65927bc92f

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I37da2b3b2da697701b883bff9a1eff2772352844

Merge "doc: Improve contribution guidelines" into integration

Merge "Add Chris Kay as code owner for CMake Build Definitions." into integration

Add Chris Kay as code owner for CMake Build Definitions. ...

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I69365d4aed1160af41e291f6e4b1dd31cbd12e02

Merge "maintainers: step down as code owner of UniPhier platform" into integration

Merge "Remove Jack Bond-Preston as CMake Build Definitions code owner" into integration

maintainers: step down as code owner of UniPhier platform ...

I am leaving Socionext. Orphan the UniPhier platform until somebody
takes the role.

Change-Id: I54d3da6d49c1ccaaa475431654db578b683db88a
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

Remove Jack Bond-Preston as CMake Build Definitions code owner ...

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I542ec3cf1bb929a5656dda6dbad816b69837c646

doc: Update the cot-binding for nv-counter node ...

Updated the cot-binding documentation to add 'id'
property for the trusted and non-trusted nv-counters.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: If1c628c5b90fe403dd96c7cd0cd04f37288c965c

doc: Improve contribution guidelines ...

- Add some guidance about the type of information a patch author should
  provide to facilitate the review (and for future reference).

- Make a number of implicit expectations explicit:
  - Every patch must compile.
  - All CI tests must pass.

- Mention that the patch author is expected to add reviewers and explain
  how to choose them.

- Explain the patch submission rules in terms of Gerrit labels.

Also do some cosmetic changes, like adding empty lines, shuffling some
paragraphs around.

Change-Id: I6dac486684310b5a35aac7353e10fe5474a81ec5
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "doc: Minor formatting improvement in the coding guidelines document" into integration

doc: Recommend using C rather than assembly language ...

Add a section for that in the coding guidelines.

Change-Id: Ie6819c4df5889a861460eb96acf2bc9c0cfb494e
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge changes from topic "at_errata_fix" into integration ...

* changes:
  doc: Update description for AT speculative workaround
  lib/cpus: Report AT speculative erratum workaround
  Add wrapper for AT instruction

doc: Minor formatting improvement in the coding guidelines document ...

Change-Id: I5362780db422772fd547dc8e68e459109edccdd0
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

qemu/qemu_sbsa: enable SPM support ...

Enable the spm_mm framework for the qemu_sbsa platform.
Memory layout required for spm_mm is created in secure SRAM.

Co-developed-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Change-Id: I104a623e8bc1e44d035b95f014a13b3f8b33a62a

doc: Update description for AT speculative workaround ...

Documented the CPU specific build macros created for AT
speculative workaround.

Updated the description of 'ERRATA_SPECULATIVE_AT' errata
workaround option.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie46a80d4e8183c1d5c8b153f08742a04d41a2af2

Merge "plat/arm: Use common build flag for using generic sp804 driver" into integration

plat/arm: Use common build flag for using generic sp804 driver ...

SP804 TIMER is not platform specific, and current code base adds
multiple defines to use this driver. Like FVP_USE_SP804_TIMER and
FVP_VE_USE_SP804_TIMER.

This patch removes platform specific build flag and adds generic
flag `USE_SP804_TIMER` to be set to 1 by platform if needed.

Change-Id: I5ab792c189885fd1b98ddd187f3a38ebdd0baba2
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

doc: Refactor the contribution guidelines ...

Ensuring that each file changed by a patch has the correct copyright and
license information does not only apply to documentation files but to
all files within the source tree.

Move the guidance for copyright and license headers out of the paragraph
about updating the documentation to avoid any confusion.

Also do some cosmetic changes (adding empty lines, fitting in longer
lines in the 80-column limit, ...) to improve the readability of the RST
file.

Change-Id: I241a2089ca9db70f5a9f26b7070b947674b43265
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

doc: Mention the TF-A Tech Forum as a way to contact developers ...

Change-Id: Ib4ad853ebb6e28adcf9ed14714d43799f9370343
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

doc: Emphasize that security issues must not be reported as normal bugs ...

Change-Id: I43e452c9993a8608b20ec029562982f5dcf8e6b2
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

doc: Stop advising the creation of Phabricator issues ...

We have noticed that Phabricator (the ticketing system on tf.org [1])
has far less visibility within the community than the mailing list [2].
For this reason, let's drop usage of Phabricator for anything else than
bug reports. For the rest, advise contributors to start a discussion on
the mailing list, where they are more likely to get feedback.

[1] https://developer.trustedfirmware.org/project/board/1/
[2] https://lists.trustedfirmware.org/mailman/listinfo/tf-a

Change-Id: I7d2d3d305ad0a0f8aacc2a2f25eb5ff429853a3f
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

Merge "TF-A AMU extension: fix detection of group 1 counters." into integration

Merge changes from topic "release/14.0" into integration ...

* changes:
  docs: marvell: update PHY porting layer description
  docs: marvell: update path in marvell documentation
  docs: marvell: update build instructions with CN913x
  plat: marvell: octeontx: add support for t9130
  plat: marvell: t9130: add SVC support
  plat: marvell: t9130: update AVS settings
  plat: marvell: t9130: pass actual CP count for load_image
  plat: marvell: armada: a7k: add support to SVC validation mode
  plat: marvell: armada: add support for twin-die combined memory device

Merge "sc7180 platform support" into integration

TF-A AMU extension: fix detection of group 1 counters. ...

This patch fixes the bug when AMUv1 group1 counters was
always assumed being implemented without checking for its
presence which was causing exception otherwise.
The AMU extension code was also modified as listed below:
- Added detection of AMUv1 for ARMv8.6
- 'PLAT_AMU_GROUP1_NR_COUNTERS' build option is removed and
number of group1 counters 'AMU_GROUP1_NR_COUNTERS' is now
calculated based on 'AMU_GROUP1_COUNTERS_MASK' value
- Added bit fields definitions and access functions for
AMCFGR_EL0/AMCFGR and AMCGCR_EL0/AMCGCR registers
- Unification of amu.c Aarch64 and Aarch32 source files
- Bug fixes and TF-A coding style compliant changes.

Change-Id: I14e407be62c3026ebc674ec7045e240ccb71e1fb
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>