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History for arm-trusted-firmware / fdts

2020-12-31	3ec0ddd Browse files » Import USB DFU programmer from ST ... This commit imports, squashes and fixes up the following commits by ST: `110dad1` stm32mp1: add USB programmer `d6c7f1f` plat/st: initialize dev_status with correct status `78ddbb9` io: io_programmer_st_usb: improve timeout management in usb loop It excludes the code for the UART programmer. I used it this way: make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_USB_PROGRAMMER=1 DTB_FILE_NAME=stm32mp157c-dk2.dtb DEBUG=1 dfu-util -d 0483:df11 -a 1 -D build/stm32mp1/debug/tf-a-stm32mp157c-dk2.stm32 dfu-util -d 0483:df11 -a 0 -D build/stm32mp1/debug/tf-a-stm32mp157c-dk2.stm32 dfu-util -d 0483:df11 -a 3 -D ~/barebox/images/barebox-stm32mp157c-seeed-odyssey.img dfu-util -d 0483:df11 -e -a 0 Jookia committed on 31 Dec 2020
	a80e6f4 Browse files » fdts: stm32mp157ca-dk1: Support using PLL4 as Ethernet clock ... This enables the internal Ethernet clock and sets PLL4 to 750Mhz so operating systems can clock PLL4_P to 125MHz and use it for Ethernet. Jookia committed on 31 Dec 2020
	90ec3ee Browse files » fdts: Move PMIC to I2C2 and eMMC to SDMMC2 ... This is a quick hack to work with the Seeed STM32MP157C SoM Jookia committed on 31 Dec 2020
2020-10-20	a3ecbb3 Browse files » plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS ... - Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1 - Add TC0_NS_DRAM1 base and mapping - Reserve memory region in tc0.dts Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13 Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com> Arunachalam Ganapathy authored on 22 Sep 2020 Manish Pandey committed on 20 Oct 2020
2020-10-13	b37b52e Browse files » fdts: add missing hash node in STM32MP157C-ED1 board DT ... Without this node, the board fails to boot and panics in the function stm32mp_init_auth(). Change-Id: Ia54924410dac2a8c94dd6e45d7e93977fe7d87e2 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 13 Oct 2020
2020-10-12	0c3e8ac Browse files » drivers: stm32_fmc2_nand: move to new bindings ... FMC node bindings are modified to add EBI controller node. FMC driver and associated device tree files are modified to support these new bindings. Change-Id: I4bf201e96a1aca20957e0dac3a3b87caadd05bdc Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Christophe Kerello authored on 16 Jul 2020 Lionel Debieve committed on 12 Oct 2020
2020-10-08	390181a Browse files » fdts: enable virtio-rng component for morello fvp platform ... enable virtio-rng component for morello fvp platform Change-Id: I89b950f067a4d14dfa418de3859c88c8f91cf7c5 Signed-off-by: Jagadeesh Ujja <jagadeesh.ujja@arm.com> Jagadeesh Ujja committed on 8 Oct 2020
2020-10-02	dc57bea Browse files » Merge "fdts: stm32mp1: realign device tree with kernel" into integration Madhukar Pappireddy authored on 2 Oct 2020 TrustedFirmware Code Review committed on 2 Oct 2020
2020-09-29	2173b3e Browse files » Merge changes from topic "fpga_generic" into integration ... * changes: arm_fpga: Add platform documentation arm_fpga: Add post-build linker script arm_fpga: Add ROM trampoline arm_fpga: Add devicetree file arm_fpga: Remove SPE PMU DT node if SPE is not available arm_fpga: Adjust GICR size in DT to match number of cores fdt: Add function to adjust GICv3 redistributor size drivers: arm: gicv3: Allow detecting number of cores André Przywara authored on 29 Sep 2020 TrustedFirmware Code Review committed on 29 Sep 2020
2020-09-29	b48883c Browse files » arm_fpga: Add devicetree file ... The FPGA images used in Arm Ltd. focus on CPU cores, so they share a common platform, with a minimal set of peripherals (interconnect, GIC, UART). This allows to support most platforms with a single devicetree file. The topology and number of CPU cores differ, but those will added at runtime, in BL31. Other adjustments (GICR size, SPE node, command line) are also done at this point. Add the common devicetree file to TF-A's build system, so it can be build together with BL31. At runtime, the resulting .dtb file should be uploaded to the address given with FPGA_PRELOADED_DTB_BASE at build time. Change-Id: I3206d6131059502ec96896e95329865452c9d83e Signed-off-by: Andre Przywara <andre.przywara@arm.com> Andre Przywara committed on 29 Sep 2020
2020-09-28	e1cbcf9 Browse files » fdts: add device tree sources for morello platform ... Change-Id: Ib5945c37983505f327a195bdb8b91ed1b7b90921 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com> Manoj Kumar authored on 31 Jul 2020 Chandni Cherukuri committed on 28 Sep 2020
2020-09-24	277d6af Browse files » fdts: stm32mp1: realign device tree with kernel ... There is one dtsi file per SoC version: - STM32MP151: common part for all version, Single Cortex-A7 - STM32MP153: Dual Cortex-A7 - STM32MP157: + GPU and DSI, but not needed for TF-A The STM32MP15xC include a cryptography peripheral, add it in a dedicated file. There are 4 packages available, for which the IOs number change. Have one file for each package. The 2 packages AB and AD are added. STM32157A-DK1 and STM32MP157C-DK2 share most of their features, a common dkx file is then created. Some reordering is done in other files, and realign with kernel DT files. The DDR files are generated with our internal tool, no changes in the registers values. Change-Id: I9f2ef00306310abe34b94c2f10fc7a77a10493d1 Signed-off-by: Yann Gautier <yann.gautier@st.com> Yann Gautier committed on 24 Sep 2020
2020-09-22	Unverified 8f734c6 Browse files » fdts: tc0: update MHUv2 interrupt number ... This is as part of the architecture change in TC0. Change-Id: I470241f67938e7998941d26f0e8bc05073234152 Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 22 Sep 2020
2020-09-16	35d626b Browse files » n1sdp: add support for remote chip pcie. ... Remote chip ITS, SMMU, PCIe nodes are added for enabling remote chip PCIe hierarchy. Change-Id: I5b3ca733715defa38e413588ccd13d0688cba271 Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com> Sayanta Pattanayak authored on 31 Jul 2020 Khasim Syed Mohammed committed on 16 Sep 2020
2020-09-15	a6f65b1 Browse files » Merge "fdts: corstone700: add NXP isp1763 node to device tree" into integration Manish Pandey authored on 15 Sep 2020 TrustedFirmware Code Review committed on 15 Sep 2020
2020-09-08	0dc5229 Browse files » Enabling DPU in dts file for TC0 ... This change replaces hdlcd with DPU in dts file for TC0 Change-Id: If25dfd3ddffc07279ab487f65e1bb82b27a26604 Signed-off-by: Avinash Mehta <avinash.mehta@arm.com> Avinash Mehta authored on 22 Jul 2020 Anders Dellien committed on 8 Sep 2020
2020-09-07	23875c3 Browse files » fdts: corstone700: add NXP isp1763 node to device tree ... Add USB IP node as the MPS3 board has the NXP isp1763 host controller. Change-Id: I47c57e4c8345d244c46895b52fcaecc1c6f1b504 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: lakshmi Kailasanathan <lakshmi.Kailasanathan@arm.com> Rui Miguel Silva authored on 15 Jul 2020 lakshmi Kailasanathan committed on 7 Sep 2020
2020-09-02	ee99356 Browse files » Merge "dtsi: Update the nv-counter node in the device tree" into integration Alexei Fedorov authored on 2 Sep 2020 TrustedFirmware Code Review committed on 2 Sep 2020
2020-08-28	699d8a1 Browse files » dtsi: Update the nv-counter node in the device tree ... Created a header file defining the id of the various nv-counters used in the system. Also, updated the device tree to add 'id' property for the trusted and non-trusted nv-counters. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ia41a557f7e56ad4ed536aee11c7a59e078ae07c0 Manish V Badarkhe authored on 23 Aug 2020 Manish V Badarkhe committed on 28 Aug 2020
2020-08-27	Unverified 8ea4f80 Browse files » fdts: tc0: add support for cpu-idle-states ... This includes both cpu and cluster sleep parameters. Change-Id: I6a9e90b88508d6d2acd2538007cbbdd1cf976442 Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 27 Aug 2020
2020-08-27	Unverified a41973a Browse files » fdts: tc0: Add node for mmc ... The pl180 mmc uses 3.3V fixed regulator and vexpress sysreg for card detection and write protect. Change-Id: I2513cfcb97217e282a081a700f3a9f723e8207ff Signed-off-by: Usama Arif <usama.arif@arm.com> Usama Arif committed on 27 Aug 2020
2020-08-04	070632f Browse files » Merge "SPM: build OP-TEE as an S-EL1 Secure Partition" into integration Manish Pandey authored on 4 Aug 2020 TrustedFirmware Code Review committed on 4 Aug 2020
2020-07-31	03a5225 Browse files » tbbr/dualroot: rename SP package certificate file ... Currently only single signing domain is supported for SP packages but there is plan to support dual signing domains if CoT is dualroot. SP_CONTENT_CERT_ID is the certificate file which is currently generated and signed with trusted world key which in-turn is derived from Silicon provider RoT key. To allow dual signing domain for SP packages, other certificate file will be derived from Platform owned RoT key. This patch renames "SP_CONTENT_CERT_ID" to "SIP_SP_CONTENT_CERT_ID" and does other related changes. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I0bc445a3ab257e2dac03faa64f46e36a9fed5e93 Manish Pandey committed on 31 Jul 2020
2020-07-30	db1ef41 Browse files » SPM: build OP-TEE as an S-EL1 Secure Partition ... Provide manifest and build options to boot OP-TEE as a guest S-EL1 Secure Partition on top of Hafnium in S-EL2. Increase ARM_SP_MAX_SIZE to cope with OP-TEE debug build image. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Idd2686fa689a78fe2d05ed92b1d23c65e2edd4cb Olivier Deprez committed on 30 Jul 2020
2020-07-30	000653b Browse files » fdts: n1sdp: DTS file for single-chip and multi-chip environment. ... N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Andre Przywara authored on 6 Jul 2020 Sayanta Pattanayak committed on 30 Jul 2020
2020-07-10	567bfe5 Browse files » dts: Add CoT descriptor nodes and properties in device tree ... Added CoT descriptor nodes and properties in device tree. Currently, CoT descriptors which are used by BL2 are added as part of device tree. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0 Manish V Badarkhe authored on 29 Jun 2020 Sandrine Bailleux committed on 10 Jul 2020
2020-07-06	ef93cfa Browse files » corstone700: splitting the platform support into FVP and FPGA ... This patch performs the following: - Creating two corstone700 platforms under corstone700 board: fvp and fpga - Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform - The platform can be specified using the TARGET_PLATFORM Makefile variable (possible values are: fvp or fpga) - Allowing to use u-boot by: - Enabling NEED_BL33 option - Fixing non-secure image base: For no preloaded bl33 we want to have the NS base set on shared ram. Setup a memory map region for NS in shared map and set the bl33 address in the area. - Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected platform - Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163 Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com> Abdellatif El Khlifi committed on 6 Jul 2020
2020-06-09	452d5e5 Browse files » plat/fvp: Add support for dynamic description of secure interrupts ... Using the fconf framework, the Group 0 and Group 1 secure interrupt descriptors are moved to device tree and retrieved in runtime. This feature is enabled by the build flag SEC_INT_DESC_IN_FCONF. Change-Id: I360c63a83286c7ecc2426cd1ff1b4746d61e633c Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Madhukar Pappireddy committed on 9 Jun 2020
2020-06-03	bca652a Browse files » dts: stm32mp157c: fix etzpc node location in DTSI file ... Fix etzpc node location in stm32mp157c DTSI file as requested during the patch review. The comment was addressed then fixup change discarded while rebasing. Change-Id: Ie53531fec7da224de0b86c968a66aec441bfc25d Fixes: 627298d4b655 ("dts: stm32mp157c: add etzpc node") Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Etienne Carriere committed on 3 Jun 2020
2020-06-03	627298d Browse files » dts: stm32mp157c: add etzpc node ... Add a node for the ETZPC device so that driver initializes during stm32mp15* boot sequence. Change-Id: I84bf10572e5df7b8f450163c79bcfe6956fc838f Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Etienne Carriere committed on 3 Jun 2020