LuminaSensum/arm-trusted-firmware

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History for arm-trusted-firmware / plat

2020-12-31	3ec0ddd Browse files » Import USB DFU programmer from ST ... This commit imports, squashes and fixes up the following commits by ST: `110dad1` stm32mp1: add USB programmer `d6c7f1f` plat/st: initialize dev_status with correct status `78ddbb9` io: io_programmer_st_usb: improve timeout management in usb loop It excludes the code for the UART programmer. I used it this way: make CROSS_COMPILE=arm-none-eabi- PLAT=stm32mp1 ARCH=aarch32 ARM_ARCH_MAJOR=7 AARCH32_SP=sp_min STM32MP_SDMMC=1 STM32MP_EMMC=1 STM32MP_USB_PROGRAMMER=1 DTB_FILE_NAME=stm32mp157c-dk2.dtb DEBUG=1 dfu-util -d 0483:df11 -a 1 -D build/stm32mp1/debug/tf-a-stm32mp157c-dk2.stm32 dfu-util -d 0483:df11 -a 0 -D build/stm32mp1/debug/tf-a-stm32mp157c-dk2.stm32 dfu-util -d 0483:df11 -a 3 -D ~/barebox/images/barebox-stm32mp157c-seeed-odyssey.img dfu-util -d 0483:df11 -e -a 0 Jookia committed on 31 Dec 2020
2020-10-29	8109d2d Browse files » Merge "Use constant stack size with RECLAIM_INIT_CODE" into integration Alexei Fedorov authored on 29 Oct 2020 TrustedFirmware Code Review committed on 29 Oct 2020
2020-10-29	271708e Browse files » Merge changes from topic "mbox-patches" into integration ... * changes: intel: common: Fix non-MISRA compliant code v2 intel: mailbox: Fix non-MISRA compliant code intel: mailbox: Mailbox error recovery handling intel: mailbox: Enable sending large mailbox command intel: mailbox: Use retry count in mailbox poll intel: mailbox: Ensure time out duration is predictive intel: mailbox: Read mailbox response even there is an error intel: mailbox: Driver now handles larger response intel: common: Change how mailbox handles job id & buffer intel: common: Improve readability of mailbox read response intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB intel: common: Remove urgent from mailbox async intel: common: Improve mailbox driver readability Manish Pandey authored on 29 Oct 2020 TrustedFirmware Code Review committed on 29 Oct 2020
2020-10-28	3ed5606 Browse files » Use constant stack size with RECLAIM_INIT_CODE ... Currently, when RECLAIM_INIT_CODE is set, the stacks are scaled to ensure that the entirety of the init section can be reclaimed as stack. This causes an issue in lib/psci/aarch64/psci_helpers.S, where the stack size is used for cache operations in psci_do_pwrdown_cache_maintenance(). If the stacks are scaled, then the PSCI code may fail to invalidate some of the stack memory before power down. Resizing stacks is also not good for stability in general, since code that works with a small number of cores may overflow the stack when the number of cores is increased. Change to make every stack be PLATFORM_STACK_SIZE big, and allow the total stack to be smaller than the init section. Any pages of the init section not reclaimed as stack will be set to read-only and execute-never, for security. Change-Id: I10b3884981006431f2fcbec3864c81d4a8c246e8 Signed-off-by: David Horstmann <david.horstmann@arm.com> David Horstmann committed on 28 Oct 2020
	6e97b22 Browse files » Merge changes from topic "mbox-patches" into integration ... * changes: intel: common: Clean up mailbox and sip header intel: clear 'PLAT_SEC_ENTRY' in early platform setup Manish Pandey authored on 28 Oct 2020 TrustedFirmware Code Review committed on 28 Oct 2020
	350c04f Browse files » Merge changes I07448d85,If85be70b,Ie6802d6d,I67a9abef into integration ... * changes: mediatek: mt8192: add timer support mediatek: mt8192: Add reboot function for PSCI mediatek: mt8192: add sys_cirq driver mediatek: mt8192: add GPIO driver support Manish Pandey authored on 28 Oct 2020 TrustedFirmware Code Review committed on 28 Oct 2020
	4a12801 Browse files » mediatek: mt8192: add timer support ... add timer driver. Signed-off-by: Dehui Sun <dehui.sun@mediatek.com> Change-Id: I07448d85a15bb14577b05e4f302860d609420ba7 Dehui Sun authored on 2 Jul 2020 Nina Wu committed on 28 Oct 2020
	0f40824 Browse files » mediatek: mt8192: Add reboot function for PSCI ... Add system_reset function in psci ops Change-Id: If85be70b8ae9d6487e02626356f0ff1e78b76de9 Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com> Nina Wu committed on 28 Oct 2020
	b6cec33 Browse files » mediatek: mt8192: add sys_cirq driver ... 1.add sys_cirq driver 2.add gic api for cirq Change-Id: Ie6802d6ddcf7dde3412a050736dfdc85f97cb51b Signed-off-by: gtk_pangao <gtk_pangao@mediatek.com> gtk_pangao authored on 19 Dec 2019 Nina Wu committed on 28 Oct 2020
2020-10-27	c036570 Browse files » Merge "plat: marvell: armada: Fix dependences for target fip" into integration Manish Pandey authored on 27 Oct 2020 TrustedFirmware Code Review committed on 27 Oct 2020
2020-10-26	d57318b Browse files » intel: common: Fix non-MISRA compliant code v2 ... This patch is used to fix remaining non compliant code for Intel SoCFPGA's mailbox and sip driver. These changes include: - Change non-interface required uint32_t into unsigned int - Change non-negative variable to unsigned int - Remove obsolete variable initialization to 0 Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I3a16c7621a5fc75eb614d97d72e44c86e7d53bf5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9e28590 Browse files » intel: mailbox: Fix non-MISRA compliant code ... This patch is used to fix remaining non compliant code for Intel SocFPGA's mailbox driver. These changes include: - adding integer literal for unsigned constant - fix non-boolean controlling expression - add braces even on conditional single statement bodies Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0f8fd96a3540f35ee102fd2f2369b76fa73e39e1 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	9975604 Browse files » intel: mailbox: Mailbox error recovery handling ... Attempt to restart the mailbox if the mailbox driver not able to write any data into the mailbox command buffer. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: Ia45291c985844dec9da82839cac701347534d32b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d14e965 Browse files » intel: mailbox: Enable sending large mailbox command ... Allow mailbox command that is larger than mailbox command FIFO buffer size to be sent to SDM in multiple chunks. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I683d5f1d04c4fdf57d11ecae6232b7ed3fc49e26 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	4978bc2 Browse files » intel: mailbox: Use retry count in mailbox poll ... Change the main loop inside mailbox poll function from while(1) to a retry counter named sdm_loop. This is to limit the maximum possible looping of the function and prevent unexpected behaviour. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I63afad958fe5f656f6333b60d5a8b4c0ada3b23d Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	d96e7cd Browse files » intel: mailbox: Ensure time out duration is predictive ... For each count down of time out counter, wait for number of miliseconds to ensure the time out duration is predictive. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I0e92dd1ef1da0ef504ec86472cf0d3c88528930b Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	6d9f9f5 Browse files » intel: mailbox: Read mailbox response even there is an error ... Mailbox driver should read the response data if the response length in the response header is non-zero even the response header indicates error (non-zero). Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I928f705f43c0f46ac74b84428b830276cc4c9640 Chee Hong Ang authored on 10 May 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	39aebd3 Browse files » intel: mailbox: Driver now handles larger response ... This patch factorizes mailbox read response from SDM into a function. Also fix the logic to support reading larger than 16 words response from SDM. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ie035ecffbbc42e12dd68061c403904c28c3b70e5 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	aad868b Browse files » intel: common: Change how mailbox handles job id & buffer ... This patch modifies several basic mailbox driver features to prepare for FCS enablement: - Job id management for asynchronous response - SDM command buffer full Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I78168dfb6c521d70d9cba187356b7a3c8e9b62d2 Abdul Halim, Muhammad Hadi Asyrafi committed on 26 Oct 2020
	00ad74c Browse files » Merge "SPMC: adjust device region for first secure partition" into integration Olivier Deprez authored on 26 Oct 2020 TrustedFirmware Code Review committed on 26 Oct 2020
	054af8f Browse files » mediatek: mt8192: add GPIO driver support ... add GPIO driver Change-Id: I67a9abef078e7a62b34dfbd366b45c03892800cd Signed-off-by: Po Xu <jg_poxu@mediatek.com> Po Xu committed on 26 Oct 2020
2020-10-23	516f322 Browse files » intel: common: Clean up mailbox and sip header ... Sort and rearrange definitions in both mailbox and sip header to increase readability and maintainability. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5544c2f17efdf3174757c55afd8cc1062fbae856 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	941fc5c Browse files » intel: common: Improve readability of mailbox read response ... Rename variables to improve readability of mailbox read response and mailbox poll response flow. Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Icd33ff1d2abb28eeead15e4eb9c7f9629f8cb402 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	7f56f24 Browse files » intel: clear 'PLAT_SEC_ENTRY' in early platform setup ... Ensure 'PLAT_SEC_ENTRY' is cleared during early platform setup. This is to prevent the slave CPU cores jump to the stale entry point after warm reset when using U-Boot SPL as first stage boot loader. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Change-Id: I3294ce2f74aa691d0cf311fa30f27f9d4fb8800a Chee Hong Ang authored on 24 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	1ae7b6f Browse files » intel: SIP: increase FPGA_CONFIG_SIZE to 32 MB ... Increase INTEL_SIP_SMC_FPGA_CONFIG_SIZE from 16 to 32MB. We need higher pre-reserved memory size between Intel service layer and secure monitor software so we can handle JIC file authorization. Signed-off-by: Richard Gong <richard.gong@intel.com> Change-Id: Ibab4e42e4b7b93a4cf741e60ec9439359ba0a64c Richard Gong authored on 13 Apr 2020 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	d191eb2 Browse files » intel: common: Remove urgent from mailbox async ... Remove urgent argument from asynchrounous mailbox command as any urgent command should always be synchronous Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Iaa64335db24df3a562470d0d1c3d6a3a71493319 Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	f8e6a09 Browse files » intel: common: Improve mailbox driver readability ... Use pre-defined macros for return values and common mailbox arguments Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5d549ee5358aebadf909f79fda55e83ee9844a0e Abdul Halim, Muhammad Hadi Asyrafi committed on 23 Oct 2020
	9c28689 Browse files » Merge changes I5ae9d08b,I5cbbd7eb,Idb389223 into integration ... * changes: plat: marvell: armada: Building ${DOIMAGETOOL} is only for a8k plat: marvell: armada: Fix including plat/marvell/marvell.mk file plat: marvell: armada: a3k: When WTP is empty do not define variables and targets which depends on it Varun Wadekar authored on 23 Oct 2020 TrustedFirmware Code Review committed on 23 Oct 2020
2020-10-22	083dbb6 Browse files » Merge "plat/qemu_sbsa: Remove cortex_a53 and aem_generic" into integration Manish Pandey authored on 22 Oct 2020 TrustedFirmware Code Review committed on 22 Oct 2020
2020-10-21	d0d63af Browse files » SPMC: adjust device region for first secure partition ... For the first partition, mark first 2GB as device memory excluding the Trusted DRAM region reserved for the SPMC. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I3ff110b3facf5b6d41ac2519ff6ca5e30a0a502b Olivier Deprez committed on 21 Oct 2020