// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2015, The Linux Foundation. All rights reserved.
*/
/dts-v1/;
#include <dt-bindings/clock/qcom,gcc-ipq4019.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
#address-cells = <1>;
#size-cells = <1>;
model = "Qualcomm Technologies, Inc. IPQ4019";
compatible = "qcom,ipq4019";
interrupt-parent = <&intc>;
reserved-memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
smem_region: smem@87e00000 {
reg = <0x87e00000 0x080000>;
no-map;
};
tz@87e80000 {
reg = <0x87e80000 0x180000>;
no-map;
};
};
aliases {
spi0 = &blsp1_spi1;
spi1 = &blsp1_spi2;
i2c0 = &blsp1_i2c3;
i2c1 = &blsp1_i2c4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
reg = <0x0>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
reg = <0x3>;
clocks = <&gcc GCC_APPS_CLK_SRC>;
clock-frequency = <0>;
clock-latency = <256000>;
operating-points-v2 = <&cpu0_opp_table>;
};
L2: l2-cache {
compatible = "cache";
cache-level = <2>;
qcom,saw = <&saw_l2>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp-48000000 {
opp-hz = /bits/ 64 <48000000>;
clock-latency-ns = <256000>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
clock-latency-ns = <256000>;
};
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
clock-latency-ns = <256000>;
};
opp-716000000 {
opp-hz = /bits/ 64 <716000000>;
clock-latency-ns = <256000>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x0>;
};
pmu {
compatible = "arm,cortex-a7-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_HIGH)>;
};
clocks {
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
xo: xo {
compatible = "fixed-clock";
clock-frequency = <48000000>;
#clock-cells = <0>;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq4019";
};
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <48000000>;
always-on;
};
soc {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "simple-bus";
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-ipq4019";
#clock-cells = <1>;
#reset-cells = <1>;
reg = <0x1800000 0x60000>;
};
rng@22000 {
compatible = "qcom,prng";
reg = <0x22000 0x140>;
clocks = <&gcc GCC_PRNG_AHB_CLK>;
clock-names = "core";
status = "disabled";
};
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq4019-pinctrl";
reg = <0x01000000 0x300000>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 100>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
sdhci: sdhci@7824900 {
compatible = "qcom,sdhci-msm-v4";
reg = <0x7824900 0x11c>, <0x7824000 0x800>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
bus-width = <8>;
clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_DCD_XO_CLK>;
clock-names = "core", "iface", "xo";
status = "disabled";
};
blsp_dma: dma@7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 5>, <&blsp_dma 4>;
dma-names = "rx", "tx";
status = "disabled";
};
blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 7>, <&blsp_dma 6>;
dma-names = "rx", "tx";
status = "disabled";
};
blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 9>, <&blsp_dma 8>;
dma-names = "rx", "tx";
status = "disabled";
};
blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 11>, <&blsp_dma 10>;
dma-names = "rx", "tx";
status = "disabled";
};
cryptobam: dma@8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <1>;
qcom,controlled-remotely;
status = "disabled";
};
crypto@8e3a000 {
compatible = "qcom,crypto-v5.1";
reg = <0x08e3a000 0x6000>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
<&gcc GCC_CRYPTO_AXI_CLK>,
<&gcc GCC_CRYPTO_CLK>;
clock-names = "iface", "bus", "core";
dmas = <&cryptobam 2>, <&cryptobam 3>;
dma-names = "rx", "tx";
status = "disabled";
};
acc0: clock-controller@b088000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
};
acc1: clock-controller@b098000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
};
acc2: clock-controller@b0a8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
};
acc3: clock-controller@b0b8000 {
compatible = "qcom,kpss-acc-v2";
reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
};
saw0: regulator@b089000 {
compatible = "qcom,saw2";
reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw1: regulator@b099000 {
compatible = "qcom,saw2";
reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw2: regulator@b0a9000 {
compatible = "qcom,saw2";
reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw3: regulator@b0b9000 {
compatible = "qcom,saw2";
reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
regulator;
};
saw_l2: regulator@b012000 {
compatible = "qcom,saw2";
reg = <0xb012000 0x1000>;
regulator;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 1>, <&blsp_dma 0>;
dma-names = "rx", "tx";
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
dmas = <&blsp_dma 3>, <&blsp_dma 2>;
dma-names = "rx", "tx";
};
watchdog@b017000 {
compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
reg = <0xb017000 0x40>;
clocks = <&sleep_clk>;
timeout-sec = <10>;
status = "disabled";
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
};
pcie0: pci@40000000 {
compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
reg = <0x40000000 0xf1d
0x40000f20 0xa8
0x80000 0x2000
0x40100000 0x1000>;
reg-names = "dbi", "elbi", "parf", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
<0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
<0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
<0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
<0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
clocks = <&gcc GCC_PCIE_AHB_CLK>,
<&gcc GCC_PCIE_AXI_M_CLK>,
<&gcc GCC_PCIE_AXI_S_CLK>;
clock-names = "aux",
"master_bus",
"slave_bus";
resets = <&gcc PCIE_AXI_M_ARES>,
<&gcc PCIE_AXI_S_ARES>,
<&gcc PCIE_PIPE_ARES>,
<&gcc PCIE_AXI_M_VMIDMT_ARES>,
<&gcc PCIE_AXI_S_XPU_ARES>,
<&gcc PCIE_PARF_XPU_ARES>,
<&gcc PCIE_PHY_ARES>,
<&gcc PCIE_AXI_M_STICKY_ARES>,
<&gcc PCIE_PIPE_STICKY_ARES>,
<&gcc PCIE_PWR_ARES>,
<&gcc PCIE_AHB_ARES>,
<&gcc PCIE_PHY_AHB_ARES>;
reset-names = "axi_m",
"axi_s",
"pipe",
"axi_m_vmid",
"axi_s_xpu",
"parf",
"phy",
"axi_m_sticky",
"pipe_sticky",
"pwr",
"ahb",
"phy_ahb";
status = "disabled";
};
qpic_bam: dma@7984000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x7984000 0x1a000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QPIC_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
status = "disabled";
};
nand: qpic-nand@79b0000 {
compatible = "qcom,ipq4019-nand";
reg = <0x79b0000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcc GCC_QPIC_CLK>,
<&gcc GCC_QPIC_AHB_CLK>;
clock-names = "core", "aon";
dmas = <&qpic_bam 0>,
<&qpic_bam 1>,
<&qpic_bam 2>;
dma-names = "tx", "rx", "cmd";
status = "disabled";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-bus-width = <8>;
};
};
wifi0: wifi@a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
resets = <&gcc WIFI0_CPU_INIT_RESET>,
<&gcc WIFI0_RADIO_SRIF_RESET>,
<&gcc WIFI0_RADIO_WARM_RESET>,
<&gcc WIFI0_RADIO_COLD_RESET>,
<&gcc WIFI0_CORE_WARM_RESET>,
<&gcc WIFI0_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init", "wifi_radio_srif",
"wifi_radio_warm", "wifi_radio_cold",
"wifi_core_warm", "wifi_core_cold";
clocks = <&gcc GCC_WCSS2G_CLK>,
<&gcc GCC_WCSS2G_REF_CLK>,
<&gcc GCC_WCSS2G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
"wifi_wcss_rtc";
interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
};
wifi1: wifi@a800000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa800000 0x200000>;
resets = <&gcc WIFI1_CPU_INIT_RESET>,
<&gcc WIFI1_RADIO_SRIF_RESET>,
<&gcc WIFI1_RADIO_WARM_RESET>,
<&gcc WIFI1_RADIO_COLD_RESET>,
<&gcc WIFI1_CORE_WARM_RESET>,
<&gcc WIFI1_CORE_COLD_RESET>;
reset-names = "wifi_cpu_init", "wifi_radio_srif",
"wifi_radio_warm", "wifi_radio_cold",
"wifi_core_warm", "wifi_core_cold";
clocks = <&gcc GCC_WCSS5G_CLK>,
<&gcc GCC_WCSS5G_REF_CLK>,
<&gcc GCC_WCSS5G_RTC_CLK>;
clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
"wifi_wcss_rtc";
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
"msi12", "msi13", "msi14", "msi15",
"legacy";
status = "disabled";
};
mdio: mdio@90000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "qcom,ipq4019-mdio";
reg = <0x90000 0x64>;
status = "disabled";
ethphy0: ethernet-phy@0 {
reg = <0>;
};
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
ethphy3: ethernet-phy@3 {
reg = <3>;
};
ethphy4: ethernet-phy@4 {
reg = <4>;
};
};
};
};
