#include <dt-bindings/clock/ath79-clk.h>

/ {
	compatible = "qca,ar9344";

	#address-cells = <1>;
	#size-cells = <1>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "mips,mips74Kc";
			clocks = <&pll ATH79_CLK_CPU>;
			reg = <0>;
		};
	};

	ref: ref {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};

	ahb {
		compatible = "simple-bus";
		ranges;

		#address-cells = <1>;
		#size-cells = <1>;

		apb {
			compatible = "simple-bus";
			ranges;

			#address-cells = <1>;
			#size-cells = <1>;

			uart0: uart@18020000 {
				compatible = "ns16550a", "qca,ar9344-uart0";
				reg = <0x18020000 0x20>;

				reg-shift = <2>;
				reg-io-width = <4>;
				big-endian;

				status = "disabled";
			};

			pll: pll-controller@18050000 {
				compatible = "qca,ar9344-pll";
				reg = <0x18050000 0x100>;

				clocks = <&ref>;
				clock-names = "ref";

				#clock-cells = <1>;
			};

			spi: spi@1f000000 {
				compatible = "qca,ar7100-spi", "qca,ar9344-spi";
				reg = <0x1f000000 0x1c>;

				#address-cells = <1>;
				#size-cells = <0>;

				status = "disabled";
			};
		};

		mac0: mac@19000000 {
			compatible = "qca,ar9344-gmac0";
			reg = <0x18070000 0x00000100>,
			      <0x19000000 0x01000000>;
			reg-names = "gmac", "ge0";
			phy-mode = "rgmii";

			status = "disabled";
		};
	};
};