# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A83t DWC HDMI TX Encoder Device Tree Bindings
description: |
The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller
IP with Allwinner\'s own PHY IP. It supports audio and video outputs
and CEC.
These DT bindings follow the Synopsys DWC HDMI TX bindings defined
in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
the following device-specific properties.
maintainers:
- Chen-Yu Tsai <wens@csie.org>
- Maxime Ripard <mripard@kernel.org>
properties:
"#phy-cells":
const: 0
compatible:
oneOf:
- const: allwinner,sun8i-a83t-dw-hdmi
- const: allwinner,sun50i-h6-dw-hdmi
- items:
- enum:
- allwinner,sun8i-h3-dw-hdmi
- allwinner,sun8i-r40-dw-hdmi
- allwinner,sun50i-a64-dw-hdmi
- const: allwinner,sun8i-a83t-dw-hdmi
reg:
maxItems: 1
reg-io-width:
const: 1
interrupts:
maxItems: 1
clocks:
minItems: 3
maxItems: 6
items:
- description: Bus Clock
- description: Register Clock
- description: TMDS Clock
- description: HDMI CEC Clock
- description: HDCP Clock
- description: HDCP Bus Clock
clock-names:
minItems: 3
maxItems: 6
items:
- const: iahb
- const: isfr
- const: tmds
- const: cec
- const: hdcp
- const: hdcp-bus
resets:
minItems: 1
maxItems: 2
items:
- description: HDMI Controller Reset
- description: HDCP Reset
reset-names:
minItems: 1
maxItems: 2
items:
- const: ctrl
- const: hdcp
phys:
maxItems: 1
description:
Phandle to the DWC HDMI PHY.
phy-names:
const: phy
hvcc-supply:
description:
The VCC power supply of the controller
ports:
type: object
description: |
A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
properties:
"#address-cells":
const: 1
"#size-cells":
const: 0
port@0:
type: object
description: |
Input endpoints of the controller. Usually the associated
TCON.
port@1:
type: object
description: |
Output endpoints of the controller. Usually an HDMI
connector.
required:
- "#address-cells"
- "#size-cells"
- port@0
- port@1
additionalProperties: false
required:
- compatible
- reg
- reg-io-width
- interrupts
- clocks
- clock-names
- resets
- reset-names
- phys
- phy-names
- ports
if:
properties:
compatible:
contains:
enum:
- allwinner,sun50i-h6-dw-hdmi
then:
properties:
clocks:
minItems: 6
clock-names:
minItems: 6
resets:
minItems: 2
reset-names:
minItems: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
/*
* This comes from the clock/sun8i-a83t-ccu.h and
* reset/sun8i-a83t-ccu.h headers, but we can't include them since
* it would trigger a bunch of warnings for redefinitions of
* symbols with the other example.
*/
#define CLK_BUS_HDMI 39
#define CLK_HDMI 93
#define CLK_HDMI_SLOW 94
#define RST_BUS_HDMI1 26
hdmi@1ee0000 {
compatible = "allwinner,sun8i-a83t-dw-hdmi";
reg = <0x01ee0000 0x10000>;
reg-io-width = <1>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>;
clock-names = "iahb", "isfr", "tmds";
resets = <&ccu RST_BUS_HDMI1>;
reset-names = "ctrl";
phys = <&hdmi_phy>;
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&tcon1_out_hdmi>;
};
};
port@1 {
reg = <1>;
};
};
};
/* Cleanup after ourselves */
#undef CLK_BUS_HDMI
#undef CLK_HDMI
#undef CLK_HDMI_SLOW
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
/*
* This comes from the clock/sun50i-h6-ccu.h and
* reset/sun50i-h6-ccu.h headers, but we can't include them since
* it would trigger a bunch of warnings for redefinitions of
* symbols with the other example.
*/
#define CLK_BUS_HDMI 126
#define CLK_BUS_HDCP 137
#define CLK_HDMI 123
#define CLK_HDMI_SLOW 124
#define CLK_HDMI_CEC 125
#define CLK_HDCP 136
#define RST_BUS_HDMI_SUB 57
#define RST_BUS_HDCP 62
hdmi@6000000 {
compatible = "allwinner,sun50i-h6-dw-hdmi";
reg = <0x06000000 0x10000>;
reg-io-width = <1>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
<&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
<&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
"hdcp-bus";
resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>;
reset-names = "ctrl", "hdcp";
phys = <&hdmi_phy>;
phy-names = "phy";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
};
};
port@1 {
reg = <1>;
};
};
};
...
