/*
* Copyright (c) 2017 MediaTek Inc.
* Author: Mars.C <mars.cheng@mediatek.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <dt-bindings/clock/mt6797-clk.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "mediatek,mt6797";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
psci {
compatible = "arm,psci-0.2";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x000>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x001>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x002>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x003>;
};
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
};
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
};
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
};
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
};
cpu8: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x200>;
};
cpu9: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
enable-method = "psci";
reg = <0x201>;
};
};
clk26m: oscillator@0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
topckgen: topckgen@10000000 {
compatible = "mediatek,mt6797-topckgen";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infrasys: infracfg_ao@10001000 {
compatible = "mediatek,mt6797-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
scpsys: scpsys@10006000 {
compatible = "mediatek,mt6797-scpsys";
#power-domain-cells = <1>;
reg = <0 0x10006000 0 0x1000>;
clocks = <&topckgen CLK_TOP_MUX_MFG>,
<&topckgen CLK_TOP_MUX_MM>,
<&topckgen CLK_TOP_MUX_VDEC>;
clock-names = "mfg", "mm", "vdec";
infracfg = <&infrasys>;
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
};
apmixedsys: apmixed@1000c000 {
compatible = "mediatek,mt6797-apmixedsys";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
sysirq: intpol-controller@10200620 {
compatible = "mediatek,mt6797-sysirq",
"mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10220620 0 0x20>,
<0 0x10220690 0 0x10>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART0>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART1>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART2>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
uart3: serial@11005000 {
compatible = "mediatek,mt6797-uart",
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infrasys CLK_INFRA_UART3>,
<&infrasys CLK_INFRA_AP_DMA>;
clock-names = "baud", "bus";
status = "disabled";
};
mmsys: mmsys_config@14000000 {
compatible = "mediatek,mt6797-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
imgsys: imgsys_config@15000000 {
compatible = "mediatek,mt6797-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
vdecsys: vdec_gcon@16000000 {
compatible = "mediatek,mt6797-vdecsys", "syscon";
reg = <0 0x16000000 0 0x10000>;
#clock-cells = <1>;
};
vencsys: venc_gcon@17000000 {
compatible = "mediatek,mt6797-vencsys", "syscon";
reg = <0 0x17000000 0 0x1000>;
#clock-cells = <1>;
};
gic: interrupt-controller@19000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
reg = <0 0x19000000 0 0x10000>, /* GICD */
<0 0x19200000 0 0x200000>, /* GICR */
<0 0x10240000 0 0x2000>; /* GICC */
};
};
