/*
* Copyright (c) 2018 Protonic Holland
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
#include <arm/imx6qp.dtsi>
#include "imx6qdl-prti6q.dtsi"
/ {
model = "Protonic WD3 board";
compatible = "prt,prtwd3", "fsl,imx6qp";
memory@10000000 {
device_type = "memory";
reg = <0x10000000 0x20000000>;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
aliases {
mdio-gpio0 = &mdio0;
};
usdhc2_wifi_pwrseq: usdhc2_wifi_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wifi_npd>;
reset-gpios = <&gpio6 10 GPIO_ACTIVE_LOW>;
};
clk20m_can: fdcan_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
clk25m_switch: switch_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk25m_phy3: phy3_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
clk50m_phy: phy_clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
};
mdio0: mdio {
compatible = "virtual,mdio-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mdio0>;
#address-cells = <1>;
#size-cells = <0>;
gpios = <&gpio5 6 GPIO_ACTIVE_HIGH
&gpio5 7 GPIO_ACTIVE_HIGH>;
};
display_panel0 {
compatible = "kyo,tcg121xglp";
backlight = <&backlight_lcd>;
port {
display_panel0_in: endpoint {
remote-endpoint = <&serializer0_out>;
};
};
};
display_panel1 {
compatible = "kyo,tcg121xglp";
backlight = <&backlight_panel1>;
port {
display_panel1_in: endpoint {
remote-endpoint = <&serializer1_out>;
};
};
};
backlight_lcd: backlight_lcd {
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>;
default-brightness-level = <15>;
power-supply = <®_3v3>;
};
backlight_panel1: backlight_panel1 {
compatible = "pwm-backlight";
pwms = <&pwm2 0 5000000>;
brightness-levels = <0 1 2 4 6 8 12 16 24 32 48 64 96 128 192 255>;
default-brightness-level = <0>;
power-supply = <®_3v3>;
};
};
&fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
status = "okay";
clocks = <&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET>,
<&clks IMX6QDL_CLK_ENET_REF>,
<&clks IMX6QDL_CLK_ENET_REF>;
clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
assigned-clock-rates = <125000000>;
phy-mode = "rgmii";
fixed-link {
speed = <100>;
full-duplex;
};
mdio1: mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Microchip KSZ9031 */
rgmii_phy: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <2>;
interrupts-extended = <&gpio1 28 IRQ_TYPE_EDGE_FALLING>;
/* FIXME: tx/rx clk skew are currently set by imx
* platform driver. Write own walues here to not depend
* fixup of horror.
*/
reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
/* reset assert time is provided by documentation */
reset-assert-us = <10000>;
/* documented reset deassert time (100us) is not enough
* use test value of 300us.
*/
reset-deassert-us = <1000>;
clocks = <&clk25m_phy3>;
};
};
};
&ecspi2 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
sja1105_switch: sja1105@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
compatible = "nxp,sja1105q";
spi-max-frequency = <4000000>;
spi-cpha;
spi-rx-delay-us = <1>;
spi-tx-delay-us = <1>;
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
clocks = <&clk25m_switch>;
#clock-cells = <1>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "usb";
phy-handle = <&usbeth_phy>;
phy-mode = "rmii";
};
port@1 {
reg = <1>;
label = "t1slave";
phy-handle = <&tja1102_phy1>;
phy-mode = "rmii";
};
port@2 {
reg = <2>;
label = "t1master";
phy-handle = <&tja1102_phy0>;
phy-mode = "rmii";
};
port@3 {
reg = <3>;
label = "rj45";
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-id";
};
port@4 {
reg = <4>;
label = "cpu";
ethernet = <&fec>;
phy-mode = "rgmii-id";
fixed-link {
speed = <100>;
full-duplex;
};
};
};
};
};
&mdio0 {
usbeth_phy: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x3>;
interrupts-extended = <&gpio5 12 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <0>;
reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
reset-assert-us = <500>;
reset-deassert-us = <1000>;
/* FIXME: the clock is provided by switch and we should know
* and we should request it only after switch have done clock
* configuration. Since it is currently not implemented,
* use fixed clock.
* WARNING: Using fixed clocks in this case is potential source
* for evil bugs. Switch may reconfigure, stop or change clk
* freq without letting PHY to know about it.
*/
clocks = <&clk50m_phy>;
clock-names = "rmii-ref";
};
tja1102_phy0: ethernet-phy@4 {
compatible = "ethernet-phy-id0180.dc80";
reg = <0x4>;
interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
/* reset detection time is 20 usec. */
reset-assert-us = <20>;
/* reset to standby 2 msec. */
reset-deassert-us = <2000>;
#address-cells = <1>;
#size-cells = <0>;
tja1102_phy1: ethernet-phy@5 {
reg = <0x5>;
interrupts-extended = <&gpio5 8 IRQ_TYPE_LEVEL_LOW>;
};
};
};
&ecspi3 {
fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
can3: can@0 {
compatible = "microchip,mcp2518fd";
spi-max-frequency = <5000000>;
reg = <0>;
clocks = <&clk20m_can>;
interrupt-parent = <&gpio4>;
interrupts = <25 0x2>;
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
serializer0: ds90ub927@c {
compatible = "ti,ds90ub927";
reg = <0x0c>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
serializer0_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
/* port@1 {
reg = <1>;
serializer0_audio_in: endpoint {
remote-endpoint = <&audio_i2s0_out>;
};
}; */
port@2 {
reg = <2>;
serializer0_out: endpoint {
remote-endpoint = <&display_panel0_in>;
};
};
};
};
&i2c2 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
serializer1: ds90ub927@c {
compatible = "ti,ds90ub927";
reg = <0x0c>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
serializer1_in: endpoint {
remote-endpoint = <&lvds1_out>;
};
};
port@2 {
reg = <2>;
serializer1_out: endpoint {
remote-endpoint = <&display_panel1_in>;
};
};
};
camdeser: ds90ub954@30 {
compatible = "ti,ds90ub954";
reg = <0x30>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
camdeser_fpd_link_in: endpoint {
};
};
port@1 {
reg = <1>;
camdeser_mipi_out: endpoint {
remote-endpoint = <&mipi_csi_in>;
};
};
};
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
no-1-8-v; /* force 3.3V VIO */
non-removable;
mmc-pwrseq = <&usdhc2_wifi_pwrseq>;
pm-ignore-notify;
status = "okay";
#address-cells = <1>;
#size-cells = <0>;
brcmf: bcrmf@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
};
};
&i2c3 {
adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
channel@4 {
reg = <4>;
ti,gain = <1>;
ti,datarate = <3>;
};
channel@5 {
reg = <5>;
ti,gain = <1>;
ti,datarate = <3>;
};
channel@6 {
reg = <6>;
ti,gain = <1>;
ti,datarate = <3>;
};
channel@7 {
reg = <7>;
ti,gain = <1>;
ti,datarate = <3>;
};
};
};
&ldb {
status = "okay";
lvds-channel@0 {
status = "okay";
port@4 {
reg = <4>;
lvds0_out: endpoint {
remote-endpoint = <&serializer0_in>;
};
};
};
lvds-channel@1 {
status = "okay";
port@4 {
reg = <4>;
lvds1_out: endpoint {
remote-endpoint = <&serializer1_in>;
};
};
};
};
&mipi_csi {
status = "okay";
port@0 {
reg = <0>;
mipi_csi_in: endpoint {
remote-endpoint = <&camdeser_mipi_out>;
};
};
};
&ipu1_csi0_mux_from_parallel_sensor {
/* Empty, to disable parallel camera from PRTI6Q */
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&iomuxc {
pinctrl_enet: enetgrp {
fsl,pins = <
MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x10030
MX6QDL_PAD_ENET_MDC__ENET_MDC 0x10030
/* Configure clock provider for RGMII ref clock */
MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0b0
/* Configure clock consumer for RGMII ref clock */
MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x10030
/* SJA1105Q switch reset */
MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x10030
/* phy3/rgmii_phy reset */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x10030
/* phy3/rgmii_phy int */
MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x40010000
>;
};
pinctrl_mdio0: mdio0grp {
fsl,pins = <
/* phy0/usbeth_phy reset */
MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x10030
/* phy0/usbeth_phy int */
MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x100b1
/* phy12/tja1102_phy0 reset */
MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x10030
/* phy12/tja1102_phy0 int */
MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x100b1
/* phy12/tja1102_phy0 enable. Set 100K pull-up */
MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1f030
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x000b1
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
/* SGTL5000 sys_mclk */
MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x030b0
/* CAN1_SR + CAN2_SR GPIO outputs */
MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x13070
MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x13070
/* CAN1_TERM (not used on WD3) */
MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
/* HW revision detect */
/* REV_ID0 */
MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0
/* REV_ID1 */
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
/* REV_ID2 */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
/* REV_ID3 */
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
/* REV_ID4 */
MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
/* USB charging control */
/* CHG Control */
MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x130b0
/* RID0 */
MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x130b0
/* RID1 */
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x130b0
/* RID2 */
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x130b0
/* Power VSEL and TG */
/* VSEL */
MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x1b0b0
/* TG */
MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x1b0b0
/* Display panel 0 GPIO */
/* L/R */
MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x1b0b0
/* TS_nINT */
MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x1b0b0
/* EN */
MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x1b0b0
/* LVDS0_nINT */
MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x1b0b0
/* LVDS0_PD */
MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x1b0b0
/* Display panel 1 GPIO */
/* L/R */
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x1b0b0
/* TS_nINT */
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b0b0
/* EN */
MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x1b0b0
/* LVDS1_nINT */
MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x1b0b0
/* LVDS1_PD */
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x1b0b0
/* Camera */
/* CAM_GPIO0 */
MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x1b0b0
/* CAM_nINT */
MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x1b0b0
/* CAM_GPIO1 */
MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
/* CAM_nPD */
MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x1b0b0
/* CAM_LOCK */
MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x1b0b0
/* USB ethernet reset (asix) */
MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x1b0b0
>;
};
pinctrl_wifi_npd: wifinpd {
fsl,pins = <
/* WL_REG_ON */
MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x13069
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x170b9
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x100b9
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001f8b1
MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001f8b1
>;
};
pinctrl_leds: ledsgrp {
/* No leds */
fsl,pins = <>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
/* CS */
MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x000b1
/* CAN2_nINT */
MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x1b0b1
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b0
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b0
>;
};
};
